70 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Power Modes
Table 11-1 illustrates the power modes offered by PSoC 4.
In addition to the wakeup sources mentioned in Table 11-1, external reset (XRES) and brownout reset bring the device to
Active mode from any power mode.
11.1 Active Mode
Active mode is the primary power mode of the PSoC device. This mode provides the option to use every possible subsystem/
peripheral in the device. In this mode, the CPU is running and all the peripherals are powered. The firmware may be config-
ured to disable specific peripherals that are not in use, to reduce power consumption.
11.2 Sleep Mode
This is a CPU-centric power mode. In this mode, the Cortex-M0 CPU enters Sleep mode and its clock is disabled. It is a mode
that the device should come to very often or as soon as the CPU is idle, to accomplish low power consumption. It is identical
to Active mode from a peripheral point of view. Any enabled interrupt can cause wakeup from Sleep mode.
11.3 Deep-Sleep Mode
In Deep-Sleep mode, the CPU, SRAM, and high-speed logic are in retention. The high-frequency clocks, including HFCLK
and SYSCLK, are disabled. Optionally, the internal low-frequency (32 kHz) oscillator remains on and low-frequency peripher-
als continue to operate. Digital peripherals that do not need a clock or receive a clock from their external interface (for exam-
ple, I
2
C slave) continue to operate. Interrupts from low-speed, asynchronous or low-power analog peripherals can cause a
wakeup from Deep-Sleep mode.
The available wakeup sources are listed in Table 11-3.
Table 11-1. PSoC 4 Power Modes
Power
Mode
Description Entry Condition
Wakeup
Sources
Active Clocks
Wakeup
Action
Available Regulators
Active
Primary mode of opera-
tion; all peripherals are
available (programmable).
Wakeup from other
power modes, inter-
nal and external
resets, brownout,
power on reset
Not applicable
All (programma-
ble)
All regulators are available.
The Active digital regulator
can be disabled if external
regulation is used.
Sleep
CPU enters Sleep mode
and SRAM is in retention;
all peripherals are avail-
able (programmable).
Manual register write Any interrupt
All (programma-
ble)
Interrupt
All regulators are available.
The Active digital regulator
can be disabled if external
regulation is used.
Deep-
Sleep
All internal supplies are
driven from the Deep-
Sleep regulator. IMO and
high-speed peripherals are
off. Only the low-frequency
(32 kHz) clock is available.
Interrupts from low-speed,
asynchronous, or low-
power analog peripherals
can cause a wakeup.
Manual register write
GPIO interrupt,
I2C, watchdog
timer
ILO (32 kHz) Interrupt Deep-Sleep regulator
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