Cypress PSoC 4000 Series - Configure Clock

150 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Nonvolatile Memory Programming
Return
19.5.2 Configure Clock
This function initializes the clock necessary for flash programming and erasing operations. This API is used to ensure that the
charge pump clock (clk_pump) and the HF clock (clk_hf) are set to IMO at 48 MHz prior to calling the flash write and flash
erase APIs. The flash write and erase APIs will exit without acting on the flash and return the "Invalid Pump Clock Frequency"
status if the IMO is the source of the charge pump clock and is not 48 MHz.
Parameters
Return
Bits [31:16] 0x0000 Not used
CPUSS_SYSREQ register
Bits [15:0] 0x0000 Silicon ID opcode
Bits [31:16] 0x8000 Set SYSCALL_REQ bit
Address Return Value Description
CPUSS_SYSARG register
Bits [7:0] Silicon ID Lo
See the device datasheet for Silicon ID values for different
part numbers
Bits [15:8] Silicon ID Hi
Bits [19:16] Minor Revision Id
Bits [23:20] Major Revision Id
Bits [27:24] 0xXX Not used (don’t care)
Bits [31:28] 0xA Success status code
CPUSS_SYSREQ register
Bits [11:0] Family ID
Family ID is 0x09A for PSoC 4000
Bits [15:12] Chip Protection See the Device Security chapter on page 79
Bits [31:16] 0xXXXX Not used
Address Value to be Written Description
SRAM Address: 32’hYY (32-bit wide, word-aligned SRAM address)
Bits [7:0] 0xB6 Key1
Bits [15:8] 0xE8 Key2
Bits [31:16] 0xXXXX Don’t care
CPUSS_SYSARG register
Bits [31:0] 32’hYY
32-bit word-aligned address of the SRAM that
stores the first function parameter (key1)
CPUSS_SYSREQ register
Bits [15:0] 0x0015 Configure clock opcode
Bits [31:16] 0x8000 Set SYSCALL_REQ bit
Address Return Value Description
CPUSS_SYSARG register
Bits [31:28] 0xA Success status code
Bits [27:0] 0xXXXXXXX Not used (don’t care)
Address Value to be Written Description