PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 29
Cortex-M0 CPU
4.7.1 Address Alignment
An aligned access is an operation where a word-aligned
address is used for a word or multiple word access, or
where a half-word-aligned address is used for a half-word
access. Byte accesses are always aligned.
No support is provided for unaligned accesses on the Cor-
tex-M0 processor. Any attempt to perform an unaligned
memory access operation results in a HardFault exception.
4.7.2 Memory Endianness
The PSoC 4 Cortex-M0 uses the little-endian format, where
the least-significant byte of a word is stored at the lowest
address and the most significant byte is stored at the high-
est address.
4.8 Systick Timer
The Systick timer is integrated with the NVIC and generates
the SYSTICK interrupt. This interrupt can be used for task
management in a real-time system. The timer has a reload
register with 24 bits available to use as a countdown value.
The Systick timer uses the Cortex-M0 internal clock as a
source.
4.9 Debug
PSoC 4 contains a debug interface based on SWD; it fea-
tures four breakpoint (address) comparators and two watch-
point (data) comparators.
Table 4-4. Thumb Instruction Set
Mnemonic Brief Description
ADCS Add with carry
ADD{S}
a
Add
ADR PC-relative address to register
ANDS Bit wise AND
ASRS Arithmetic shift right
B{cc} Branch {conditionally}
BICS Bit clear
BKPT Breakpoint
BL Branch with link
BLX Branch indirect with link
BX Branch indirect
CMN Compare negative
CMP Compare
CPSID Change processor state, disable interrupts
CPSIE Change processor state, enable interrupts
DMB Data memory barrier
DSB Data synchronization barrier
EORS Exclusive OR
ISB Instruction synchronization barrier
LDM Load multiple registers, increment after
LDR Load register from PC-relative address
LDRB Load register with word
LDRH Load register with half-word
LDRSB Load register with signed byte
LDRSH Load register with signed half-word
LSLS Logical shift left
LSRS Logical shift right
MOV{S}
a
Move
MRS Move to general register from special register
MSR Move to special register from general register
MULS Multiply, 32-bit result
MVNS Bit wise NOT
NOP No operation
ORRS Logical OR
POP Pop registers from stack
PUSH Push registers onto stack
REV Byte-reverse word
REV16 Byte-reverse packed half-words
REVSH Byte-reverse signed half-word
RORS Rotate right
RSBS Reverse subtract
SBCS Subtract with carry
SEV Send event
STM Store multiple registers, increment after
STR Store register as word
STRB Store register as byte
STRH Store register as half-word
SUB{S}
a
Subtract
SVC Supervisor call
SXTB Sign extend byte
SXTH Sign extend half-word
TST Logical AND-based test
UXTB Zero extend a byte
UXTH Zero extend a half-word
WFE Wait for event
WFI Wait for interrupt
a. The ‘S’ qualifier causes the ADD, SUB, or MOV instructions to update
APSR condition flags.
Table 4-4. Thumb Instruction Set
Mnemonic Brief Description
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