PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 73
12. Watchdog Timer
The watchdog timer (WDT) is used to automatically reset the device in the event of an unexpected firmware execution path or
a brownout that compromises the CPU functionality. The WDT runs from the LFCLK, generated by the ILO. The timer must be
serviced periodically in firmware to avoid a reset. Otherwise, the timer will elapse and generate a device reset. The WDT can
be used as an interrupt source or a wakeup source in low-power modes.
12.1 Features
The WDT has these features:
■ System reset generation after a configurable interval
■ Periodic interrupt/wake up generation in Active, Sleep, and Deep-Sleep power modes
■ Features a 16-bit free-running counter
12.2 Block Diagram
Figure 12-1. Watchdog Timer Block Diagram
12.3 How It Works
The WDT asserts a hardware reset to the device on the third WDT match event, unless it is periodically serviced in firmware.
The WDT interrupt has a programmable period of up to 2048 ms. The WDT is a free-running wraparound up-counter with a
maximum of 16-bit resolution. The resolution is configurable as explained later in this section.
The WDT_COUNTER register provides the count value of the WDT. The WDT generates an interrupt when the count value in
WDT_COUNTER equals the match value stored in the WDT_MATCH register, but it does not reset the count to '0'. Instead,
the WDT keeps counting until it overflows (after 0xFFFF when the resolution is set to 16 bits) and rolls back to 0. When the
count value again reaches the match value, another interrupt is generated. Note that the match count can be changed when
the counter is running.
A bit named WDT_MATCH in the SRSS_INTR register is set whenever the WDT interrupt occurs. This interrupt must be
cleared by writing a '1' to the WDT_MATCH bit in SRSS_INTR to reset the watchdog. If the firmware does not reset the WDT
for two consecutive interrupts, the third match event will generate a hardware reset.
Watchdog
Timer
CLK
AHB
Interface
Register
CFG/
STATUS
CPU
Subsystem or
WIC
Reset Block
RESET
INTERRUPT
Low-Frequency
Clock
(LFCLK)
To Next Page
Loading...
