Cypress PSoC 4000 Series - Events Based on Trigger Inputs

PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 103
Timer, Counter, and PWM
16.2.3 Events Based on Trigger Inputs
These are the events triggered by hardware or software.
■ Reload
■ Start
■ Stop
■ Count
■ Capture/switch
Hardware triggers can be level signal, rising edge, falling edge, or both edges. Figure 16-2 shows the selection of edge detec-
tion type for any event trigger signal. The trigger control register 0 (TCPWM_CNT_TR_CTRL0) selects one of the 1416five
trigger inputs as the event signal, which includes constant '0' and '1' signals.
Any edge (rising, falling, or both) or level (high or low) can be selected for the occurrence of an event by configuring the trig-
ger control register 1 (TCPWM_CNT_TR_CTRL1). This edge/level configuration can be selected for each trigger event sepa-
rately. Alternatively, firmware can generate an event by writing to the counter command register (TCPWM_CMD), as shown in
Figure 16-2.
Figure 16-2. Trigger Signal Edge Detection
The events derived from these triggers can have different
definitions in different modes of the TCPWM block.
■ Reload: A reload event initializes and starts the counter.
❐ In UP counting mode, the count register
(TCPWM_CNT_COUNTER) is initialized with ‘0’.
❐ In DOWN counting mode, the counter is initialized
with the period value stored in the
TCPWM_CNT_PERIOD register.
❐ In UP/DOWN counting mode, the count register is
initialized with ‘0’.
❐ In quadrature mode, the reload event acts as a
quadrature index event. An index/reload event indi-
cates a completed rotation and can be used to syn-
chronize quadrature decoding.
■ Start: A start event is used to start counting; it can be
used after a stop event or after re-initialization of the
counter register to any value by software. Note that the
count register is not initialized on this event.
❐ In quadrature mode, the start event acts as quadra-
ture phase input phiB, which is explained in detail in
“Quadrature Decoder Mode” on page 112.
■ Count: A count event causes the counter to increment
or decrement, depending on its configuration.
❐ In quadrature mode, the count event acts as quadra-
ture phase input phiA.
■ Stop: A stop event stops the counter from incrementing
or decrementing. A start event will start the counting
again.
❐ In the PWM modes, the stop event acts as a kill
event. A kill event disables all the PWM output lines.
■ Capture: A capture event copies the counter register
value to the capture register and capture register value
to the buffer capture register. In the PWM modes, the
capture event acts as a switch event. It switches the val-
ues of the capture/compare and period registers with
their buffer counterparts. This feature can be used to
modulate the pulse width and frequency.
Notes
■ All trigger inputs are synchronized to the HFCLK.
■ When more than one event occurs in the same counter
clock period, one or more events may be missed. This
can happen for high-frequency events (frequencies
close to the counter frequency) and a timer configuration
in which a pre-scaled (divided) counter clock is used.
trigger control register 1
rising edge
falling edge
both
pass through
counter command
register (SW generated)
event
2
Edge
Detector
Circuit
Trigger signal
Trigger
Synchronization
System bus
clock
1
0
tr_in [4:0]
trigger control register 0
5
3