PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 45
7. I/O System
This chapter explains the PSoC
®
4 I/O system, its features, architecture, operating modes, and interrupts. The GPIO pins in
PSoC 4 are grouped into ports; a port can have a maximum of eight GPIOs. PSoC 4000 family has a maximum of 20 GPIOs
arranged in four ports.
7.1 Features
The PSoC 4 GPIOs have these features:
■ Analog and digital input and output capabilities
■ Eight drive strength modes
■ Edge-triggered interrupts on rising edge, falling edge, or on both the edges, on pin basis
■ Slew rate control
■ Hold mode for latching previous state (used for retaining I/O state in Deep-Sleep mode)
■ Selectable CMOS and low-voltage LVTTL input buffer mode
■ CapSense support
7.2 GPIO Interface Overview
PSoC 4 is equipped with analog and digital peripherals. Figure 7-1 shows an overview of the routing between the peripherals
and pins.
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