Cypress PSoC 4000 Series - 8.2 Clock Sources

56 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Clocking System
The three clock sources in the device are IMO, EXTCLK,
and ILO, as shown in Figure 8-1. The HFCLK mux selects
the HFCLK source from the EXTCLK or the IMO. The
HFCLK predivider divides the HFCLK input. The ILO
sources the LFCLK.
8.2 Clock Sources
8.2.1 Internal Main Oscillator
The internal main oscillator operates with no external com-
ponents and outputs a stable clock at frequencies
spanning24-48 MHz in 4-MHz increments. Frequencies are
selected by setting the frequency in the CLK_IMO_TRIM2
register and setting the IMO trim in the CLK_IMO_TRIM1
register The frequency setting in CLK_IMO_TRIM2 deter-
mines the IMO frequency output. Table 8-1 provides the set-
ting corresponding to the IMO frequency output. In addition
to setting the frequency in CLK_IMO_TRIM2, the user
needs to load corresponding trim values in the
CLK_IMO_TRIM1. Frequency selection follows an algorithm
to ensure no intermediate state is programmed to a value
higher than 48 MHz. Each PSoC device has IMO trim set-
tings determined during manufacturing to meet datasheet
specifications; the trim is stored in manufacturing configura-
tion data in SFLASH. There are TRIM values corresponding
to the frequency selected by the user. The TRIM values from
SFLASH are loaded in the corresponding trim registers –
CLK_IMO_TRIM1. These values may be loaded at startup
to achieve the desired configuration. Firmware can retrieve
these trim values and reconfigure the device to change the
frequency at run-time.
To configure the IMO frequency, follow this algorithm:
■ If ((new_freq  43 MHz) and (old_freq  43 MHz)),
Change CLK_IMO_TRIM2 to a lower frequency such as
24 MHz
Apply CLK_IMO_TRIM1, PWR_BG_TRIM4, and
PWR_BG_TRIM5 for the new_freq
Wait
 5 µs
Change CLK_IMO_TRIM2 to new_freq
■ else if (new_freq > old_freq),
Apply CLK_IMO_TRIM1, PWR_BG_TRIM4, and
PWR_BG_TRIM5 for new_freq
Wait
 5 µs
Change CLK_IMO_TRIM2 to new_freq
■ else
Change CLK_IMO_TRIM2 to new_freq
Wait
 5 cycles
Apply CLK_IMO_TRIM1, PWR_BG_TRIM4, and
PWR_BG_TRIM5 for new_freq
Table 8-1. IMO Frequency Configuration
CLK_IMO_TRIM2
Frequency in
MHz
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
000011 3
000100 4
000101 5
000110 6
000111 7
001000 8
001001 9
001010 10
001011 11
001100 12
001110 13
001111 14
010000 15
010001 16
010010 17
010011 18
010100 19
010101 20
010110 21
010111 22
011000 23
011001 24
011011 25
011100 26
011101 27
011110 28
011111 29
100000 30
100001 31
100010 32
100011 33
100101 34
100110 35
100111 36
101000 37
101001 38
101010 39
101011 40
101110 41
101111 42
110000 43
110001 44
110010 45
110011 46
110100 47
110101 48