Cypress PSoC 4000 Series - System Call Status

158 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Nonvolatile Memory Programming
19.6 System Call Status
At the end of every system call, a status code is written over the arguments in the CPUSS_SYSARG register. A success sta-
tus is 0xAXXXXXXX, where X indicates don’t care values or return data in the case of the system calls that return a value. A
failure status is indicated by 0xF00000XX, where XX is the failure code.
Table 19-2. System Call Status Codes
Status Code
(32-bit value in
CPUSS_SYSARG register)
Description
AXXXXXXXh
Success – The “X” denotes a don’t care value, which has a value of ‘0’ returned by the SROM, unless the
API returns parameters directly to the CPUSS_SYSARG register.
F0000001h Invalid Chip Protection Mode – This API is not available during the current chip protection mode.
F0000003h
Invalid Page Latch Address – The address within the page latch buffer is either out of bounds or the size pro-
vided is too large for the page address.
F0000004h Invalid Address – The row ID or byte address provided is outside of the available memory.
F0000005h Row Protected – The row ID provided is a protected row.
F0000007h
Resume Completed – All non-blocking APIs have completed. The resume API cannot be called until the next
non-blocking API.
F0000008h
Pending Resume – A non-blocking API was initiated and must be completed by calling the resume API,
before any other APIs may be called.
F0000009h
System Call Still In Progress – A resume or non-blocking is still in progress. The SPC ISR must fire before
attempting the next resume.
F000000Ah Checksum Zero Failed – The calculated checksum was not zero.
F000000Bh Invalid Opcode – The opcode is not a valid API opcode.
F000000Ch Key Opcode Mismatch – The opcode provided does not match key1 and key2.
F000000Eh Invalid Start Address – The start address is greater than the end address provided.
F0000012h
Invalid Pump Clock Frequency - IMO must be set to 48 MHz and HF clock source to the IMO clock source
before flash write/erase operations.