PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 117
Timer, Counter, and PWM
Figure 16-13. Timing Diagram for Center Aligned PWM (software switch event
16.3.4.3 Other Configurations
■ For asymmetric PWM, the up/down counting mode 1 should be used. This causes a TC when the counter reaches either
‘0’ or the period value. To create an asymmetric PWM, the compare register is changed at every TC (when the counter
reaches either ‘0’ or the period value), whereas the period register is only changed at every other TC (only when the coun-
ter reaches ‘0’).
■ For left-aligned PWM, use the up counting mode; configure the OV condition to set output line to '1' and CC condition to
reset the output line to '0'. See Table 16-3.
■ For right-aligned PWM, use the down counting mode; configure UN condition to reset output line to '0' and CC condition to
set the output line to '1'. See Table 16-3.
16.3.4.4 Kill Feature
The kill feature gives the ability to disable both output lines immediately. This event can be programmed to stop the counter
by modifying the PWM_STOP_ON_KILL and PWM_SYNC_KILL fields of the counter control register, as shown in Table 16-7.
Table 16-7. Field Setting for Stop on Kill Feature
PWM_STOP_ON_KILL Field Comments
0 The kill trigger temporarily blocks the PWM output line but the counter is still running.
1 The kill trigger temporarily blocks the PWM output line and the counter is also stopped.
A
B
B
A
M
M
N
N
Switch event
reload event
period buffer
period
compare
compare buffer
Counter
A
0
Switch at TC condition
B
M
N
TC
CC
line_out
M
A
PWM, center aligned, buffered (software switch event)
counter_clock
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