Cypress PSoC 4000 Series - Page 116

116 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Timer, Counter, and PWM
Figure 16-12. Timing Diagram for Center Aligned PWM
Figure 16-12 illustrates center-aligned PWM with software generated switch events:
■ Software generates a switch event only after both the period buffer and compare buffer registers are updated.
■ Because the updates of the second PWM pulse come late (after the terminal count), the first PWM pulse is repeated.
■ Note that the switch event is automatically cleared by hardware at TC after the event takes effect.
PWM center aligned buffered
new period value B, new compare value N
AB
B
A
B
A
M
M
N
NN
M
SW update of buffers
reload event
period buffer
period
compare
compare buffer
Counter
A
0
Switch at TC condition
B
M
N
TC
CC
line_out
counter_clock