Cypress PSoC 4000 Series - Page 160

160 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Nonvolatile Memory Programming
//Write load size param (64 bytes) to SRAM
REG( 0x20000004 ) = 0x0000003F;
for(i = 0; i < ROW_SIZE/4; i += 1)
{
REG( 0x20000008 + i*4 ) = 0xDADADADA;
}
/*Write the address of the key1 param to CPUSS_SYSARG reg*/
CPUSS_SYSARG_REG = 0x20000000;
/*Write the API opcode = 0x04 to CPUSS_SYSREQ.COMMAND
* register and assert the sysreq bit
*/
CPUSS_SYSREQ_REG = 0x80000004;
/*Perform Non-Blocking Write Row on Row 200 as an example.
* Write key1, key2, row id to SRAM row id = 0xC8 -> which is row 200
*/
REG( 0x20000000 ) = 0x00C8DAB6;
/*Write the address of the key1 param to CPUSS_SYSARG reg */
CPUSS_SYSARG_REG = 0x20000000;
/*Write the API opcode = 0x07 to CPUSS_SYSREQ.COMMAND
* register and assert the sysreq bit
*/
CPUSS_SYSREQ_REG = 0x80000007;
/*Execute user code until iStatusInt equals 3 to signify
* 3 SPC interrupts have happened. This should be 1 in case
* of non-blocking program System Call
*/
while( iStatusInt != 0x03 )
{
DoOtherUserStuff();
}
/* Get the success or failure status of System Call*/
syscall_status = CPUSS_SYSARG_REG;
}
In the code, the CM0 exception table is configured to be in SRAM by writing 0x01 to the CPUSS_CONFIG register. The
SRAM exception table should have the vector address of the SPC interrupt as the address of the
SpcIntHandler() function,
which is also defined to be in SRAM. See the Interrupts chapter on page 31 for details on configuring the CM0 exception table
to be in SRAM. The pseudo code for a non-blocking program system call is also similar, except that the function opcode and
parameters will differ and the iStatusInt variable should be polled for 1 instead of 3. This is because the SPC ISR will be trig-
gered only once for a non-blocking program system call.