52 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
I/O System
Figure 7-4 shows the GPIO Edge Detect block architecture.
Figure 7-4. GPIO Edge Detect Block Architecture
An edge detector is present at each pin. It is capable of
detecting rising edge, falling edge, and both edges without
reconfiguration. The edge detector is configured by writing
into the EDGE_SEL bits of the Port Interrupt Configuration
register, GPIO_PRTx_INTR_CFG, as shown in Table 7-5.
Besides the pins, edge detector is also present at the glitch
filter output. This filter can be used on one of the pins of a
port. The pin is selected by writing to the FLT_SEL field of
the GPIO_PRTx_INTR_CFG register as shown in Table 7-6.
The edge detector outputs of a port are ORed together and
then routed to the interrupt controller (NVIC in the CPU sub-
system). Thus, there is only one interrupt vector per port. On
a pin interrupt, it is required to know which pin caused an
interrupt. This is done by reading the Port Interrupt Status
register, GPIO_PRTx_INTR. This register not only includes
the information on which pin triggered the interrupt, it also
includes the pin status; it allows the CPU to read both infor-
mation in a single read operation. This register has one
more important use – to clear the interrupt. Writing ‘1’ to the
corresponding status bit clears the pin interrupt. It is impor-
tant to clear the interrupt status bit; otherwise, the interrupt
will occur repeatedly for a single trigger or respond only
once for multiple triggers, which is explained later in this
section. Also, note that when the Port Interrupt Control Sta-
tus register is read when an interrupt is occurring on the cor-
responding port, it can result in the interrupt not being
properly detected. Therefore, when using GPIO interrupts, it
is recommended to read the status register only inside the
corresponding interrupt service routine and not in any other
part of the code. Tab le 7-7 shows the Port Interrupt Status
register bit fields.
The edge detector block output is routed to the Interrupt
Source Multiplexer shown in Figure 5-3 on page 32, which
gives an option of Level and Rising Edge detect. If the Level
option is selected, an interrupt is triggered repeatedly as
long as the Port Interrupt Status register bit is set. If the Ris-
ing Edge detect option is selected, an interrupt is triggered
only once if the Port Interrupt Status register is not cleared.
Thus, it is important to clear the interrupt status bit if the
Edge Detect block is used.
Edge Detector
Edge Detector
Edge Detector
Edge Detector
Edge Detector
Edge Detector
Edge Detector
Edge Detector
Edge Detector
50 ns Glitch Filter
Interrupt
Signal
Pin 1
Pin 2
Pin 3
Pin 4
Pin 0
Pin 5
Pin 6
Pin 7
Table 7-5. Edge Detector Configuration
EDGE_SEL Configuration
00 Interrupt is disabled
01 Interrupt on Rising Edge
10 Interrupt on Falling Edge
11 Interrupt on Both Edges
Table 7-6. Glitch filter Input Selection
FLT_SEL Selected Pin
000 Pin 0 is selected
001 Pin 1 is selected
010 Pin 2 is selected
011 Pin 3 is selected
100 Pin 4 is selected
101 Pin 5 is selected
110 Pin 6 is selected
111 Pin 7 is selected
Table 7-7. Port Interrupt Status Register
GPIO_PRTx_INTR Description
0000b to 0111b
Interrupt status on pin 0 to pin 7. Writing ‘1’
to the corresponding bit clears the interrupt
1000b Interrupt status from the glitch filter
10000b to 10111 Pin 0 to Pin 7 status
11000b Glitch filter output status
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