50 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
I/O System
■ Resistive Pull-Up and Resistive Pull-Down
In the resistive pull-up and resistive pull-down mode, the GPIO will have a series resistance in both logic 1 and logic 0 output
states. The high data state is pulled up while the low data state is pulled down. This mode is used when the bus is driven by
other signals that may cause shorts.
7.3.2.2 Slew Rate Control
GPIO pins have fast and slow output slew rate options in strong drive mode; this is configured using PORT_SLOW bit of the
Port Configuration register (GPIO_PRTx_PC[25]). Slew rate is individually configurable for each port. This bit is cleared by
default and the port works in fast slew mode. This bit can be set if a slow slew rate is required. Slower slew rate results in
reduced EMI and crosstalk; hence, the slow option is recommended for low-frequency signals or signals without strict timing
constraints.
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