PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 111
Timer, Counter, and PWM
In the figure, observe that:
■ The period register contains the maximum count value.
■ Internal overflow (OV) and TC conditions are generated when the counter reaches the period value.
■ A capture event is only possible at the edges or through software. Use trigger control register 1 to configure the edge
detection.
■ Multiple capture events in a single clock cycle are handled as:
❐ Even number of capture events - no event is observed
❐ Odd number of capture events - single event is observed
This happens when the capture signal frequency is greater than the counter_clock frequency.
16.3.2.3 Configuring Counter for Capture Mode
The steps to configure the counter for Capture mode operation and the affected register bits are as follows.
1. Disable the counter by writing '0' to the COUNTER_ENABLED field of the TCPWM_CTRL register.
2. Select Capture mode by writing '010' to the MODE[26:24] field of the TCPWM_CNT_CTRL register.
3. Set the required 16-bit period in the TCPWM_CNT_PERIOD register.
4. Set clock prescaling by writing to the GENERIC[15:8] field of the TCPWM_CNT_CTRL register, as shown in Table 16-1.
5. Set the direction of counting by writing to the UP_DOWN_MODE[17:16] field of the TCPWM_CNT_CTRL register, as
shown in Ta bl e 16 -6 .
6. Counter can be configured to run either in continuous mode or one-shot mode by writing 0 or 1, respectively to the
ONE_SHOT[18] field of the TCPWM_CNT_CTRL register.
7. Set the TCPWM_CNT_TR_CTRL0 register to select the trigger that causes the event (Reload, Start, Stop, Capture, and
Count).
8. Set the TCPWM_CNT_TR_CTRL1 register to select the edge that causes the event (Reload, Start, Stop, Capture, and
Count).
9. If required, set the interrupt upon TC or CC condition, as shown in “Interrupts” on page 104.
10. Enable the counter by writing '1' to the COUNTER_ENABLED field of the TCPWM_CTRL register. A start trigger must be
provided through firmware (TCPWM_CMD register) to start the counter if the hardware start signal is not enabled.
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