90 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Inter-Integrated Circuit (I2C)
■ EC_AM_MODE (Externally Clocked Address Matching Mode): Indicates whether I2C address matching is internally
('0') or externally ('1') clocked.
■ EC_OP_MODE (Externally Clocked Operation Mode): Indicates whether the rest of the protocol operation (besides I2C
address match) is internally ('0') or externally ('1') clocked. As mentioned earlier, externally clocked operation does not
support non-EZ functionality.
These two register fields determine the functional behavior of I2C. The register fields should be set based on the required
behavior in Active, Sleep, and Deep-Sleep system power modes. Improper setting may result in faulty behavior in certain
power modes. Table 15-9 and Table 15-10 describe the settings for I2C in EZ and non-EZ mode.
15.2.7.1 I2C Non-EZ Mode of Operation
Externally clocked operation is not supported for non-EZ functionality because there is no FIFO support for this mode. So, the
EC_OP_MODE should always be set to '0' for non-EZ mode. However, EC_AM_MODE can be set to '0' or '1'. Tabl e 15 -9
gives an overview of the possibilities. The combination EC_AM_MODE = 0 and EC_OP_MODE = 1 is invalid and the block
will not respond.
EC_AM_MODE is '0' and EC_OP_MODE is '0'.
This setting only works in Active and Sleep system power modes. All the functionality of the I2C is provided in the internally
clocked domain.
EC_AM_MODE is '1' and EC_OP_MODE is '0'.
This setting works in Active, Sleep, and Deep-Sleep system power modes. I2C address matching is performed by the exter-
nally clocked logic in Active, Sleep, and Deep-Sleep system power modes. When the externally clocked logic matches the
address, it sets a wakeup interrupt cause bit, which can be used to generate an interrupt to wakeup the CPU.
■ In Active system power mode, the CPU is active and the wakeup interrupt cause is disabled (associated MASK bit is '0').
The externally clocked logic takes care of the address matching and the internally locked logic takes care of the rest of the
I2C transfer.
■ In the Sleep mode, wakeup interrupt cause can be either enabled or disabled based on the application. The remaining
operations are similar to the Active mode.
■ In the Deep-Sleep mode, the CPU is shut down and will wake up on I2C activity if the wakeup interrupt cause is enabled.
CPU wakeup up takes time and the ongoing I2C transfer is either negatively acknowledged (NACK) or the clock is
stretched. In the case of a NACK, the internally clocked logic takes care of the first I2C transfer after it wakes up. For clock
stretching, the internally clocked logic takes care of the ongoing/stretched transfer when it wakes up. The register bit
S_NOT_READY_ADDR_NACK (bit 14) of the SCB_I2C_CTRL register determines whether the externally clocked logic
performs a negative acknowledge ('1') or clock stretch ('0').
15.2.7.2 I2C EZ Operation Mode
EZ mode has three possible settings. EC_AM_MODE can be set to '0' or '1' when EC_OP_MODE is '0' and EC_AM_MODE
must be set to '1' when EC_OP_MODE is '1'. Table 15-10 gives an overview of the possibilities. The grey cells indicate a pos-
sible, yet not recommended setting because it involves a switch from the externally clocked logic (slave selection) to the inter-
Table 15-9. I2C Operation in Non-EZ Mode
I2C (Non-EZ) Mode
System Power
Mode
EC_OP_MODE = 0 EC_OP_MODE = 1
EC_AM_MODE = 0 EC_AM_MODE = 1 EC_AM_MODE = 0 EC_AM_MODE = 1
Active and Sleep
Address match using internal clock.
Operation using internal clock.
Address match using external clock.
Operation using internal clock.
Not supported
Deep-Sleep Not supported
Address match using external clock.
Operation using internal clock.
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