Cypress PSoC 4000 Series - Page 42

42 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Memory Map
Table 6-2 shows the PSoC 4 address map.
Table 6-2. PSoC 4 Address Map
Address Range Use
0x00000000 - 0x00003FFF 16 KB flash
0x0FFFF000 - 0x10000000 4 KB supervisory flash
0x20000000 - 0x200007FF 2 KB SRAM
0x40100000 - 0x4011FFFF CPU subsystem registers
0x40020000 - 0x40023FFF I/O port control (high-speed I/O matrix) registers
0x40040000- -0x40043FFF I/O port registers
0x40050000- -0x4005FFFF TCPWM registers
0x40060000- -0x4006FFFF Fixed-function I2C registers
0x40080000- -0x4008FFFF CapSense registers
0x40030000- -0x4003FFFF Power, clock, reset control registers
0xE0000000 - 0xE00FFFFF Cortex-M0 PPB registers
0xF0000000 - 0xF0000FFF CoreSight ROM