122 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Timer, Counter, and PWM
The following steps describe the process:
■ The PWM output line, ‘line_out’, is driven with '1' when
the lower 15-bit value of the counter register is smaller
than the value in the compare register (when coun-
ter[14:0] < compare[15:0]). A compare value of ‘0x8000’
or higher always results in a '1' on the PWM output line.
A compare value of ‘0’ always results in a '0' on the
PWM output line.
■ A reload event behaves similar to a start event; however,
it does not initialize the counter.
■ Terminal count is generated when the counter value
equals the period value. LFSR generates a predictable
pattern of counter values for a certain initial value. This
predictability can be used to calculate the counter value
after a certain amount of LFSR iterations ‘n’. This calcu-
lated counter value can be used as a period value and
the TC is generated after ‘n’ iterations.
■ At TC, a switch/capture event conditionally switches the
compare and period register pairs (based on the
AUTO_RELOAD_CC and AUTO_RELOAD_PERIOD
fields of the counter control register).
■ A kill event can be programmed to stop the counter as
described in previous sections.
■ One shot mode can be configured by setting the
ONE_SHOT field of the counter control register. At termi-
nal count, the counter is stopped by hardware.
■ In this mode, underflow, overflow, and trigger condition
events do not occur.
■ CC condition occurs when the counter is running and its
value equals compare value. Figure 16-18 illustrates
pseudo-random noise behavior.
■ A compare value of 0x4000 results in 50 percent duty
cycle (only the lower 15 bits of the 16- bit counter are
used to compare with the compare register value).
Figure 16-18. Timing Diagram for Pseudo-Random PWM
A capture/switch input signal may switch the values between the compare and compare buffer registers and the period and
period buffer registers. This functionality can be used to modulate between two different compare values using a trigger input
signal to control the modulation.
Note Capture/switch input signal can only be triggered by an edge (rising, falling, or both). This input signal is remembered
until the next terminal count.
16.3.6.3 Configuring Counter for Pseudo-Random PWM Mode
The steps to configure the counter for pseudo-random PWM mode of operation and the affected register bits are as follows.
1. Disable the counter by writing '0' to COUNTER_ENABLED of the TCPWM_CTRL register.
2. Select pseudo-random PWM mode by writing '110' to the MODE[26:24] field of the TCPWM_CNT_CTRL register.
3. Set the required period (16 bit) in the TCPWM_CNT_PERIOD register and buffer period value in the
TCPWM_CNT_PERIOD_BUFF register to switch values, if required.
4. Set the 16-bit compare value in the TCPWM_CNT_CC register and the buffer compare value in the
TCPWM_CNT_CC_BUFF register to switch values.
5. Set the PWM_STOP_ON_KILL and PWM_SYNC_KILL fields of the TCPWM_CNT_CTRL register as required.
6. Set the TCPWM_CNT_TR_CTRL0 register to select the trigger that causes the event (Reload, Start, Kill, and Switch).
7. Set the TCPWM_CNT_TR_CTRL1 register to select the edge that causes the event (Reload, Start, Kill, and Switch).
8. line_out and line_out_compl can be controlled by the TCPWM_CNT_TR_CTRL2 register to set, reset, or invert upon CC,
OV, and UN conditions.
9. If required, set the interrupt upon TC or CC condition, as shown in “Interrupts” on page 104.
10. Enable the counter by writing '1' to the COUNTER_ENABLED field of the TCPWM_CTRL register.
Pseudo Random PWM
reload event
compare
period
counter
line_out
0x4000
0xACE1
0xACE1
0x5670
0xAB38 0x559C
0x2ACE
0x1567
counter_clock
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