Cypress PSoC 4000 Series - Page 132

132 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
CapSense
sinking digital-to-analog converters (IDACs), as Figure 17-3
shows.
The sigma delta modulator controls the current of the 8-bit
IDAC in an on/off manner. This IDAC is known as the modu-
lation IDAC. The 7-bit IDAC, known as the compensation
IDAC, is either always on or always off.
The sigma delta converter can operate in either single IDAC
mode or dual IDAC mode. In the single IDAC mode, the
compensation IDAC is always off. In the dual IDAC mode,
the compensation IDAC is always on.
The sigma delta converter also requires an external integrat-
ing capacitor C
MOD
, as Figure 17-1 shows. The recom-
mended value of C
MOD
is 2.2 nF. PSoC 4 has a dedicated
C
MOD
pin. See the pinout in the device datasheet for details.
The sigma delta modulator maintains the voltage across
C
MOD
at V
REF
. It works in one of the following modes:
■ IDAC sourcing mode: If the switched capacitor circuit
sinks current from AMUXBUS A, the IDACs source cur-
rent to AMUXBUS A to balance its voltage.
■ IDAC sinking mode: In this mode, the IDACs sink current
from C
MOD
and the switched capacitor circuit sources
current to C
MOD
.
In both cases, the modulation IDAC current is switched on
and off corresponding to the small voltage variations across
C
MOD
to maintain the C
MOD
voltage at V
REF
.
The sigma delta converter can operate from 8-bit to 16-bit
resolutions. In the single IDAC mode, the raw count is pro-
portional to the sensor capacitance. If 'N' is the resolution of
the sigma delta converter and I
MOD
is the value of the modu-
lation IDAC current, the approximate value of raw count in
IDAC sourcing mode is given by Equation 16-7.
Equation 17-7
Similarly, the approximate value of raw count in IDAC sink-
ing mode is:
Equation 17-8
In both cases, the raw count is proportional to sensor capac-
itance C
S
. This raw count can be processed by the firmware
to detect touches. You can use both the IDACs in a dual
IDAC mode to improve the CapSense performance.
In this dual IDAC mode, the compensation IDAC is always
on. If I
COMP
is the compensation IDAC current, the equation
for the raw count in IDAC sourcing mode is:
Equation 17-9
Raw count in IDAC sinking mode is given by equation 16-10.
Equation 17-10
Note that raw count values are always positive.
The hardware parameters such as I
COMP
, I
MOD
, and F
SW
,
should be tuned to optimum values for reliable touch detec-
tion. For a detailed discussion of the tuning process, see the
PSoC 4 CapSense Design Guide.
Registers CSD_CONFIG, CSD_COUNTER, and
CSD_IDAC control the operation of the sigma delta con-
verter. The important bits in the CSD_CONFIG register are:
■ ENABLE in CSD_CONFIG: Master enable of the CSD
block. Must be set to '1' for any CSD operation.
■ POLARITY in CSD_CONFIG: Selects between IDAC
sinking mode and IDAC sourcing mode. 0: IDAC sourc-
ing mode, 1: IDAC sinking mode.
■ SENSE_COMP_BW in CSD_CONFIG: Selects the
bandwidth of the sensing comparator. Setting this bit
gives high bandwidth and clearing it gives low band-
width. High bandwidth is recommended for CSD opera-
tion.
■ SENSE_COMP_EN in CSD_CONFIG: Turns on the
sense comparator circuit. 0: Sense comparator is pow-
ered off. 1: Sense comparator is powered on.
■ SENSE_EN: Enables the sigma delta modulator output.
Also turns on the IDACs.
The IDACs must be configured properly for CSD operation.
See the CSD_IDAC register in the
PSoC 4000 Family:
PSoC 4 Registers TRM for details.
CSD_COUNTER register is used to initiate a sampling of
the currently selected sensor and to read the result. The 16-
bit COUNTER field in this register increments whenever the
comparator is sampled (at the modulation clock frequency)
and the sample is 1. Firmware typically writes ‘0’ to this field
whenever a new sense operation is initiated. The 16-bit
PERIOD field in the CSD_COUNTER register is used to ini-
tiate the capacitance to digital conversion. Writing a non-
zero value to this register initiates a sensing operation. The
value written to this field by the firmware determines the
period during which the COUNTER field samples the com-
parator output.
The clocks, GPIOs, IDACs, and the sigma delta modulator
must be properly configured before starting the CSD opera-
tion. The period field decrements after every modulation
clock cycle. When it reaches 0, the COUNTER field stops
incrementing. The value of this field at this time is the raw
count corresponding to the value of sensor capacitance.
Rawcount 2
N
V
REF
F
SW
I
MOD
-------------------------
C
S
=
Rawcount 2
N
V
DD
V
REF
–F
SW
I
MOD
-----------------------------------------------
C
S
=
Rawcount 2
N
V
REF
F
SW
I
MOD
-------------------------
C
S
2
N
I
COMP
I
MOD
----------------
–=
Rawcount 2
N
V
DD
V
REF
–F
SW
I
MOD
-----------------------------------------------
C
S
2
N
I
COMP
I
MOD
----------------
–=