Cypress PSoC 4000 Series - Page 21

PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 21
Document Construction
IRES initial power on reset
IRA interrupt request acknowledge
IRQ interrupt request
ISR interrupt service routine
IVR interrupt vector read
LCD liquid crystal display
LFCLK low-frequency clock
LPCOMP low-power comparator
LRb last received bit
LRB last received byte
LSb least significant bit
LSB least significant byte
LUT lookup table
MISO master-in-slave-out
MMIO memory mapped input/output
MOSI master-out-slave-in
MSb most significant bit
MSB most significant byte
NMI non-maskable interrupt
NVIC nested vectored interrupt controller
PC program counter
PCB printed circuit board
PCH program counter high
PCL program counter low
PD power down
PGA programmable gain amplifier
PM power management
PMA PSoC memory arbiter
POR power-on reset
PPOR precision power-on reset
PRS pseudo random sequence
PSoC
®
Programmable System-on-Chip
PSRR power supply rejection ratio
PSSDC power system sleep duty cycle
PWM pulse width modulator
RAM random-access memory
RETI return from interrupt
RF radio frequency
ROM read only memory
RMS root mean square
RW read/write
SAR successive approximation register
SC switched capacitor
SCB serial communication block
SIE serial interface engine
SIO special I/O
SE0 single-ended zero
Table 3-2. Acronyms (continued)
Acronym Definition
SNR signal-to-noise ratio
SOF start of frame
SOI start of instruction
SP stack pointer
SPD sequential phase detector
SPI serial peripheral interconnect
SPIM serial peripheral interconnect master
SPIS serial peripheral interconnect slave
SRAM static random-access memory
SROM supervisory read only memory
SSADC single slope ADC
SSC supervisory system call
SYSCLK system clock
SWD single wire debug
TC terminal count
TCPWM timer, counter, PWM
TD transaction descriptors
UART universal asynchronous receiver/transmitter
UDB universal digital block
USB universal serial bus
USBIO USB I/O
WCO watch crystal oscillator
WDT watchdog timer
WDR watchdog reset
XRES external reset
XRES_N external reset, active low
Table 3-2. Acronyms (continued)
Acronym Definition