R
12 Intel
®
82925X/82925XE MCH Datasheet
Intel
®
82925X/82925XE MCH Features
Processor Interface
⎯ One Intel
®
Pentium
®
4 processor (supports
775-land package)
⎯ Supports Pentium 4 processor FSB interrupt
delivery
⎯ 800 MT/s (200 MHz) FSB
⎯ 1066 MT/s (266 MHz) FSB (82925XE
MCH Only)
⎯ Supports Hyper-Threading Technology
(HT Technology)
Ω
⎯ FSB Dynamic Bus Inversion (DBI)
⎯ 32-bit host bus addressing for access to
4 GB of memory space
⎯ 12-deep In-Order Queue
⎯ 1-deep Defer Queue
⎯ GTL+ bus driver with integrated GTL
termination resistors
⎯ Supports a Cache Line Size of 64 bytes
⎯ Supports Intel Pentium
®
4 processors with
Intel
®
EM64T
Φ
DMI Interface
⎯ A chip-to-chip connection interface to Intel
®
ICH6
⎯ 2 GB/s point-to-point DMI to ICH6 (1 GB/s
each direction)
⎯ 100 MHz reference clock (shared with PCI
Express Graphics Attach).
⎯ 32-bit downstream addressing
⎯ Messaging and Error Handling
System Memory
⎯ One or two 64-bit wide DDR2 SDRAM
data channels
⎯ Bandwidth up to 8.5 GB/s (DDR2 533) in
dual-channel Interleaved mode
⎯ ECC (82925X MCH Only) and Non-ECC
memory
⎯ 256-Mb, 512-Mb and 1-Gb DDR2
technologies
⎯ Only x8, x16, DDR2 devices with four
banks and also supports eight bank, 1-Gbit
DDR2 devices.
⎯ Opportunistic refresh
⎯ Up to 64 simultaneously open pages (four
ranks of eight bank devices* 2 channels)
⎯ SPD (Serial Presence Detect) scheme for
DIMM detection support
⎯ Suspend-to-RAM support using CKE
⎯ Supports configurations defined in the
JEDEC DDR2 DIMM specification only
PCI Express Graphics Interface
⎯ One x16 PCI Express port
⎯ Compatible with the PCI Express Base
Specification Revision 1.0a
Package
⎯ 37.5 mm × 37.5 mm., 1210 balls, variable
ball pitch
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