NXP Semiconductors UM11227 - Page 201

NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
201 / 205
Tab. 161. SIMRS register field descriptions .................. 156
Tab. 162. SIM control register (SIMC) (address $1801) . 157
Tab. 163. SIMC register field descriptions .....................157
Tab. 164. SIM option 1 register (SIMOPT1) (address
$1802) ........................................................... 158
Tab. 165. SIMOPT1 register field descriptions .............. 158
Tab. 166. SIM option 2 register (SIMOPT2) (address
$1803) ........................................................... 159
Tab. 167. SIMOPT2 field descriptions ...........................159
Tab. 168. SIM part ID high register (SIMPID1)
(address $1806) ............................................ 160
Tab. 169. SIM part ID low register (SIMPID2) (address
$1807) ........................................................... 160
Tab. 170. SIMPID1/SIMPID2 register field
descriptions ................................................... 160
Tab. 171. SIM stop exit status register (SIMSES)
(address $180D) ........................................... 160
Tab. 172. SIMSES register field descriptions ................ 161
Tab. 173. SIM oscillator trim register (SIMOTRM)
(address $180E) ............................................161
Tab. 174. SIMOTRM register field descriptions .............162
Tab. 175. PMC real-time-interrupt status and control
register (SRTISC) (address $1808) ...............166
Tab. 176. SRTISC register field descriptions ................ 166
Tab. 177. PMC status and control 1 register
(SPMSC1) (address $1809) .......................... 167
Tab. 178. SPMSC1 register field descriptions ...............167
Tab. 179. PMC status and control 2 register
(SPMSC2) (address $180A) ..........................168
Tab. 180. SPMSC2 register field descriptions ...............168
Tab. 181. PMC status and control 3 register
(PMCSC3) (address $180C) ......................... 168
Tab. 182. PMCSC3 register field descriptions ...............169
Tab. 183. Program and erase times ..............................170
Tab. 184. FMC clock divider register (FCDIV) (address
$1820) ........................................................... 177
Tab. 185. FCDIV register field descriptions ...................177
Tab. 186. FMC clock divider register settings ............... 177
Tab. 187. FMC option registers (FOPT) (address
$1821) ........................................................... 178
Tab. 188. FMC option registers (NVOPT) (address
$FFBF) .......................................................... 178
Tab. 189. FOPT and NVOPT register field descriptions . 178
Tab. 190. FMC configuration registers (FCNFG)
(address $1823) ............................................ 179
Tab. 191. FCNFG register field descriptions ................. 179
Tab. 192. Flash protection register (FPROT) (address
$1824) ........................................................... 179
Tab. 193. Flash protection register (NVPROT)
(address $FFBD) ...........................................179
Tab. 194. FPROT and NVPROT register field
descriptions ................................................... 180
Tab. 195. FMC status register (FSTAT) (address
$1825) ........................................................... 180
Tab. 196. FMC status register (FSTAT) (address
$1825) ........................................................... 180
Tab. 197. FSTAT register field descriptions .................. 180
Tab. 198. FMC command register (FCMD) (address
$1826) ........................................................... 181
Tab. 199. FCMD register field descriptions ................... 181
Tab. 200. FCMD available flash commands ..................181
Tab. 201. FRC status and control register (FRCCR)
(address $1880) ............................................ 183
Tab. 202. FRCCR register field descriptions ................. 183
Tab. 203. FRC timer high register (FRCTIMERH)
(address $1881) ............................................ 184
Tab. 204. FRC timer low register (FRCTIMERL)
(address $1882) ............................................ 184
Tab. 205. FRCTIMERH/L register field descriptions ......184
Tab. 206. FRC compare high register (FRCCOMP2)
(address $1883) ............................................ 184
Tab. 207. FRC compare low register (FRCCOMP1)
(address $1884) ............................................ 185
Tab. 208. FRCCOMP2/1 register field descriptions .......185
Tab. 209. ADC10 channel assignments ........................ 186
Tab. 210. Revision history .............................................195
Figures
Fig. 1. Measurement signal range definitions ...............4
Fig. 2. Block diagram ................................................... 6
Fig. 3. NTM88 QFN package pinout ............................ 7
Fig. 4. NTM88 orientation at rest. .............................. 10
Fig. 5. CPU registers ..................................................11
Fig. 6. Condition code register ................................... 13
Fig. 7. BDM tool connector ........................................ 32
Fig. 8. BDC host-to-target serial bit timing ................. 34
Fig. 9. BDC target-to-host serial bit timing (Logic 1) ... 34
Fig. 10. BDM target-to-host serial bit timing (Logic 0) ... 35
Fig. 11. Interrupt stack frame ....................................... 49
Fig. 12. Clock distribution .............................................60
Fig. 13. General purpose I/O block diagram ................ 63
Fig. 14. General purpose I/O logic ............................... 63
Fig. 15. KBI block diagram ...........................................68
Fig. 16. External interrupt logic .................................... 70
Fig. 17. Timer pulse-width block diagram .....................72
Fig. 18. Periodic wake-up timer block diagram .............78
Fig. 19. Block diagram ................................................. 82
Fig. 20. NTM88 LFR state machine diagram ............... 86
Fig. 21. Manchester encoded datagram for LFPOL =
0 ...................................................................... 88
Fig. 22. Manchester encoded datagram for LFPOL =
1 ...................................................................... 88
Fig. 23. Definition of duty cycle of 40 % .......................88
Fig. 24. Impact of duty cycle on SYNC pattern ............ 89
Fig. 25. Antenna Q-factor equivalent model for the
LF envelope .................................................... 89
Fig. 26. LF envelope filtering ........................................89
Fig. 27. SYNC patterns ................................................ 90
Fig. 28. Telegram format (carrier preamble) ................ 91
Fig. 29. Radio frequency module block diagram ........ 105
Fig. 30. Data frame formats ....................................... 107