YASKAWA VIPA SPEED7 - Abbreviations

Instruction Description Page
T Transfer instructions
Ä 47
TAK Transfer instructions
Ä 47
TAN Math instructions
Ä 30
TAR Transfer instructions
Ä 47
TAR1 Transfer instructions
Ä 47
TAR2 Transfer instructions
Ä 47
TRUNC Data type conversion instructions
Ä 51
UC Block instructions
Ä 35
X Combination instructions (Bit)
Ä 55
X( Combination instructions (Bit)
Ä 55
XN Combination instructions (Bit)
Ä 55
XN( Combination instructions (Bit)
Ä 55
XOD Combination instructions (Word)
Ä 63
XOW Combination instructions (Word)
Ä 63
3.2 Abbreviations
Abbreviation Description
/FC First check bit
2# Binary constant
a Byte address
ACCU Register for processing bytes, words and double words
AR Address registers, contain the area-internal or area-crossing
addresses for the instructions addressed register-indirect
b Bit address
B area-crossing, register-indirect addressed byte
B (b1,b2) Constant, 2byte
B (b1,b2,b3,b4) Constant, 4byte
B#16# Byte hexadecimal
BR Binary result
c Operand range
C Counter
C# Counter constant (BCD-coded)
CC0 Condition code
CC1 Condition code
D area-crossing, register-indirect addressed double word
VIPA SPEED7
IL operations
Abbreviations
HB00 | OPL_SP7 | Operation list | en | 18-30 21