14.1.9 SFC 7 - DP_PRAL - Triggering a hardware interrupt on the DP master
With SFC 7 DP_PRAL you trigger a hardware interrupt on the DP master from the user
program of an intelligent slave. This interrupt starts OB 40 on the DP master. Using the
input parameter AL_INFO, you can identify the cause of the hardware interrupt. This
interrupt identifier is transferred to the DP master and you can evaluate the identifier in
OB 40 (variable OB40_POINT_ADDR). The requested hardware interrupt is uniquely
specified by the input parameters IOID and LADDR. For each configured address area in
the transfer memory, you can trigger exactly one hardware interrupt at any time.
SFC 7 DP_PRAL operates asynchronously, in other words, it is executed over several
SFC calls. You start the hardware interrupt request by calling SFC 7 with REQ = 1. The
status of the job is indicated by the output parameters RET_VAL and BUSY, see Meaning
of the Parameters REQ, RET_VAL and BUSY with Asynchronous SFCs. The job is com-
pleted when execution of OB 40 is completed on the DP master.
If you operate the DP slave as a standard slave, the job is completed as
soon as the diagnostic frame is obtained by the DP master.
The input parameters IOID and LADDR uniquely specify the job. If you have called SFC 7
DP_PRAL on a DP slave and you call this SFC again before the master has acknowl-
edged the requested hardware interrupt, the way in which the SFC reacts depends
largely on whether the new call involves the same job: if the parameters IOID and LADDR
match a job that is not yet completed, the SFC call is interpreted as a follow-on call
regardless of the value of the parameter AL_INFO, and the value W#16#7002 is entered
in RET_VAL.
Parameter Declaration Data Type Memory Area Description
REQ INPUT BOOL I, Q, M, D, L,
constant
REQ = 1: Hardware interrupt on the DP master
belonging to the slave
IOID INPUT BYTE I, Q, M, D, L,
constant
Identifier of the address area in the transfer
memory (for the perspective of the DP slave):
n B#16#00:Bit15 of LADDR specifies whether a
an input (Bit15=0) or output address (Bit15=1)
is involved.
n B#16#54: Peripheral input (PI)
n B#16#55: Peripheral output (PQ)
If a mixed module is involved, the area identifier of
the lower address must be specified. If the
addresses are the same, B#16#54 must be speci-
fied.
LAADR INPUT WORD I, Q, M, D, L,
constant
Start address of the address range in the transfer
memory (from the point of view of the DP slave).
If this is a range belonging to a mixed module,
specify the lower of the two addresses.
Description
How the SFC operates
Identifying a job
Parameters
VIPA SPEED7
Integrated Standard
System Functions > SFC 7 - DP_PRAL - Triggering a hardware interrupt on the DP master
HB00 | OPL_SP7 | Operation list | en | 18-30 652
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