Abov MC97F60128 - Page 164

164
MC97F60128
ABOV Semiconductor Co., Ltd.
TIFLAG(Timer Interrupt Flag Register) : D5H
7
6
5
4
3
2
1
0
–
–
T2OVIFR
T2IFR
T1OVIFR
T1IFR
T0OVIFR
T0IFR
–
–
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
T2OVIFR
When T2 overflow interrupt occurs, this bit becomes ‘1’. The flag is cleared only by
writing a ‘0’ to the bit. So, the flag should be cleared by software. Writing ‘1’ has no
effect.
0
T2 overflow interrupt no generation
1
T2 overflow interrupt generation
T2IFR
When T2 match interrupt occurs, this bit becomes ‘1’. The flag is cleared only by writing
a ‘0’ to the bit. So, the flag should be cleared by software. Writing ‘1’ has no effect.
0
T2 interrupt no generation
1
T2 interrupt generation
T1OVIFR
When T1 overflow interrupt occurs, this bit becomes ‘1’. The flag is cleared only by
writing a ‘0’ to the bit. So, the flag should be cleared by software. Writing ‘1’ has no
effect.
0
T1 overflow interrupt no generation
1
T1 overflow interrupt generation
T1IFR
When T1 match interrupt occurs, this bit becomes ‘1’. The flag is cleared only by writing
a ‘0’ to the bit. So, the flag should be cleared by software. Writing ‘1’ has no effect.
0
T1 interrupt no generation
1
T1 interrupt generation
T0OVIFR
When T0 overflow interrupt occurs, this bit becomes ‘1’. The flag is cleared only by
writing a ‘0’ to the bit. So, the flag should be cleared by software. Writing ‘1’ has no
effect.
0
T0 overflow interrupt no generation
1
T0 overflow interrupt generation
T0IFR
When T0 match interrupt occurs, this bit becomes ‘1’. The flag is cleared only by writing
a ‘0’ to the bit. So, the flag should be cleared by software. Writing ‘1’ has no effect.
0
T0 interrupt no generation
1
T0 interrupt generation