Abov MC97F60128 - Page 226

226
MC97F60128
ABOV Semiconductor Co., Ltd.
SPI2SRH (SPI 2 Status High Register) : 4087H (XSFR)
7
6
5
4
3
2
1
0
–
WCOL2
SS_HIGH2
–
FXCH2
SPI2SSEN
–
DOR2
–
R/W
R/W
–
R/W
R/W
–
R/W
Initial value : 00H
WCOL2
This bit is set if any data are written to the data register SPI2DR during transfer in the
master mode and during the SPI2 Tx FIFO is full. This bit is cleared by writing ‘0’.
0
No collision
1
Collision
SS_HIGH2
When the SS2 pin is configured as input, if “HIGH” signal comes into the pin, this flag bit
will be set.
0
Cleared when ‘0’ is written
1
No effect when ‘1’ is written
FXCH2
SPI 2 port function exchange control bit.
0
No effect
1
Exchange MOSI2 and MISO2 function
SPI2SSEN
This bit controls the SS2 pin operation
0
Disable
1
Enable (The corresponding pin should be a normal input)
DOR2
This bit is set if data are received during the SPI2 Rx FIFO full. While this bit is set, the
incoming data frame is ignored.
0
No Data OverRun
1
Data OverRun detected