Abov MC97F60128 - Page 228

228
MC97F60128
ABOV Semiconductor Co., Ltd.
SPI2CRH (SPI 2 Control High Register) : 408FH (XSFR)
7
6
5
4
3
2
1
0
SPI2EN
FLSB2
SPI2MS
CPOL2
CPHA2
SPI2DSCR
SPI2SCR1
SPI2SCR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
SPI2EN
This bit controls the SPI 2 operation
0
Disable SPI 2 operation
1
Enable SPI 2 operation
FLSB2
This bit selects the data transmission sequence
0
MSB first
1
LSB first
SPI2MS
This bit selects whether Master or Slave mode
0
Slave mode
1
Master mode
CPOL2
CPHA2
This two bits control the serial clock (SCK2) mode.
Clock polarity (CPOL2) bit determine SCK2’s value at idle mode.
Clock phase (CPHA2) bit determine if data are sampled on the leading or trailing edge
of SCK2.
CPOL2
CPHA2
Leading edge
Trailing edge
0
0
Sample (Rising)
Setup (Falling)
0
1
Setup (Rising)
Sample (Falling)
1
0
Sample (Falling)
Setup (Rising)
1
1
Setup (Falling)
Sample (Rising)
SPI2DSCR
SPI2SCR [1:0]
These three bits select the SCK2 rate of the device configured as a master. When
DSCR bit is written one, SCK2 will be doubled in master mode.
SPI2DSCR
SPI2SCR 1
SPI2SCR 0
SCK2 frequency
0
0
0
fx/4
0
0
1
fx/16
0
1
0
fx/64
0
1
1
fx/128
1
0
0
fx/2
1
0
1
fx/8
1
1
0
fx/32
1
1
1
fx/64