Abov MC97F60128 User Manual

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MC97F60128
ABOV Semiconductor Co., Ltd.
UARTnST (UARTn Status Register) : 4063H/406BH/4073H (XSFR), Where n = 2, 3 and 4
7
6
5
4
3
2
1
0
UDREn
TXCn
RXCn
WAKEn
SOFTRSTn
DORn
FEn
PEn
R/W
R/W
R
R/W
R/W
R
R/W
R/W
Initial value : 80H
UDREn
The UDREn flag indicates if the transmit buffer (UARTnDR) is ready to receive new
data. If UDREn is ‘1’, the buffer is empty and ready to be written. This flag can generate
a UDREn interrupt. Write ‘1’ has no effect.
0
Transmit buffer is not empty.
1
Transmit buffer is empty.
TXCn
This flag is set when the entire frame in the transmit shift register has been shifted out
and there is no new data currently present in the transmit buffer. This flag is
automatically cleared when the interrupt service routine of a TXCn interrupt is executed.
This flag can generate a TXCn interrupt. Write ‘1’ has no effect.
0
Transmission is ongoing.
1
Transmit buffer is empty and the data in transmit shift register are shifted out
completely.
RXCn
This flag is set when there are unread data in the receive buffer and cleared when all
the data in the receive buffer are read. The RXCn flag can be used to generate a RXCn
interrupt. Write ‘1’ has no effect.
0
There is no data unread in the receive buffer
1
There are more than 1 data in the receive buffer
WAKEn
This flag is set when the RXDn pin is detected low while the CPU is in stop mode. This
flag can be used to generate a WAKEn interrupt. This bit should be cleared by program
software. Write ‘1’ has no effect.
0
No WAKEn interrupt is generated.
1
WAKEn interrupt is generated.
SOFTRSTn
This is an internal reset and only has effect on UARTn. Writing ‘1’ to this bit initializes
the internal logic of UARTn and this bit is automatically cleared.
0
No operation
1
Reset UARTn
DORn
This bit is set if a Data OverRun occurs. While this bit is set, the incoming data frame is
ignored. This flag is valid until the receive buffer is read.
0
No Data OverRun
1
Data OverRun detected
FEn
This bit is set if the first stop bit of next character in the receive buffer is detected as ‘0’.
This bit is valid until the receive buffer is read.
0
No Frame Error
1
Frame Error detected
PEn
This bit is set if the next character in the receive buffer has a Parity Error to be received
while Parity Checking is enabled. This bit is valid until the receive buffer is read.
0
No Parity Error
1
Parity Error detected

Abov MC97F60128 Specifications

General

Brand	Abov
Model	MC97F60128
Category	Microcontrollers
Language	English