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ABOV Semiconductor Co., Ltd.
8. This is ACK signal processing stage for data packet transmitted by master. I2C holds the SCLn LOW. When
I2C loses bus mastership while transmitting data arbitrating other masters, the MLOSTn bit in USInST2 is set.
If then, I2C waits in idle state. When the data in USInDR is transmitted completely, I2C generates TENDn
interrupt.
I2C can choose one of the following cases regardless of the reception of ACK signal from slave.
1) Master receives ACK signal from slave, so continues data transfer because slave can receive more data
from master. In this case, load data to transmit to USInDR.
2) Master STOP data transfer even if it receives ACK signal from slave. In this case, set the STOPCn bit in
USInCR4.
3) Master transmits repeated START condition with not checking ACK signal. In this case, load SLAn+R/W
into the USInDR and set the STARTCn bit in USInCR4.
After doing one of the actions above, clear to “0b” all interrupt source bits in USInST2 to release SCLn line. In
case of 1), move to step 7. In case of 2), move to step 9 to handle STOP interrupt. In case of 3), move to
step 6 after transmitting the data in USInDR and if transfer direction bit is ‘1’ go to master receiver section.
9. This is the final step for master transmitter function of I2C, handling STOP interrupt. The STOP bit indicates
that data transfer between master and slave is over. To clear USInST2, write “0” to USInST2. After this, I2C
enters idle state.
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