Abov MC97F60128

279
MC97F60128
ABOV Semiconductor Co., Ltd.
USInSCLR (USI0/1 SCL Low Period Register: For I2C mode) : 403DH/404DH (XSFR), n = 0 and 1
7
6
5
4
3
2
1
0
USInSCLR7
USInSCLR6
USInSCLR5
USInSCLR4
USInSCLR3
USInSCLR2
USInSCLR1
USInSCLR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 3FH
USInSCLR[7:0]
This register defines the high period of SCL when it operates in I2C master mode.
The base clock is SCLK, the system clock and the period is calculated by the formula:
t
SCLK
X (4 X USInSCLR +2) where t
SCLK
is the period of SCLK.
USInSAR (USI0/1 Slave Address Register: For I2C mode) : 403FH/404FH (XSFR), n = 0 and 1
7
6
5
4
3
2
1
0
USInSLA6
USInSLA5
USInSLA4
USInSLA3
USInSLA2
USInSLA1
USInSLA0
USInGCE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
USInSLA[6:0]
These bits configure the slave address of I2C when it operates in I2C slave mode.
USInGCE
This bit decides whether I2C allows general call address or not in I2C slave mode.
0
Ignore general call address
1
Allow general call address