Abov MC97F60128 User Manual

280
MC97F60128
ABOV Semiconductor Co., Ltd.
USInCR1 (USI0/1 Control Register 1: For UART, SPI and I2C mode) : 4030H/4040H (XSFR), n = 0 and 1
7
6
5
4
3
2
1
0
USInMS1
USInMS0
USInPM1
USInPM0
USInS2
USInS1
ORDn
USInS0
CPHAn
CPOLn
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
USInMS[1:0]
Selects operation mode of USIn
USInMS1
USInMS0
Operation mode
0
0
Asynchronous Mode (UART)
0
1
Synchronous Mode (UART)
1
0
I2C mode
1
1
SPI mode
USInPM[1:0]
Selects parity generation and check methods (only UART mode)
USInPM1
USInPM0
Parity
0
0
No Parity
0
1
Reserved
1
0
Even Parity
1
1
Odd Parity
USInS[2:0]
When in asynchronous or synchronous mode of operation,
selects the length of data bits in frame
USInS2
USInS1
USInS0
Data Length
0
0
0
5 bit
0
0
1
6 bit
0
1
0
7 bit
0
1
1
8 bit
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
9 bit
ORDn
This bit in the same bit position with USInS1. The MSB of the data byte is transmitted
first when set to ‘1’ and the LSB when set to ‘0’ (only SPI mode)
0
LSB-first
1
MSB-first
CPOLn
This bit determines the clock polarity of ACK in synchronous or SPI mode.
0
TXD change@Rising Edge, RXD change@Falling Edge
1
TXD change@Falling Edge, RXD change@Rising Edge
CPHAn
This bit is in the same bit position with USInS0. This bit determines if data are sampled
on the leading or trailing edge of SCK (only SPI mode).
CPOLn
CPHAn
Leading edge
Trailing edge
0
0
Sample (Rising)
Setup (Falling)
0
1
Setup (Rising)
Sample (Falling)
1
0
Sample (Falling)
Setup (Rising)
1
1
Setup (Falling)
Sample (Rising)
CPOLn
This bit determines the clock polarity of ACK in synchronous or SPI mode.
0
TXD change@Rising Edge, RXD change@Falling Edge
1
TXD change@Falling Edge, RXD change@Rising Edge

Abov MC97F60128 Specifications

General

Brand	Abov
Model	MC97F60128
Category	Microcontrollers
Language	English