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ABOV Semiconductor Co., Ltd.
USInST2 (USI0/1 Status Register 2: For I2C mode) : 4039H/4049H (XSFR), n = 0 and 1
Initial value : 00H
This bit has different meaning depending on whether I2C is master or slave. When I2C
is a master, this bit represents whether it received AACK (address ACK) from slave.
No AACK is received (Master mode)
AACK is received (Master mode)
When I2C is a slave, this bit is used to indicated general call.
General call address is not detected (Slave mode)
General call address is detected (Slave mode)
This bit is set when 1-byte of data is transferred completely
1 byte of data is not completely transferred
1 byte of data is completely transferred
This bit is set when a STOP condition is detected.
No STOP condition is detected
STOP condition is detected
This bit is set when I2C is addressed by other master.
I2C is not selected as a slave
I2C is addressed by other master and acts as a slave
This bit represents the result of bus arbitration in master mode.
I2C maintains bus mastership
I2C maintains bus mastership during arbitration process
This bit reflects bus status.
I2C bus is idle, so a master can issue a START condition
This bit is used to indicate whether I2C is transmitter or receiver.
This bit shows the state of ACK signal
ACK is received at ninth SCL period
NOTE)
1. The GCALLn, TENDn, STOPDn, SSELn, and MLOSTn bits can be
source of interrupt.
2. When an I2C interrupt occurs except for STOP mode, the SCLn line is
hold LOW. To release SCLn, Clear to “0b” all interrupt source bits in
USInST2 register.
3. The GCALLn, TENDn, STOPDn, SSELn, MLOSTn, and RXACKn bits
are cleared when “0b” is written to the corresponding bit.
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