EasyManua.ls Logo

Abov MC97F60128 - Page 292

Abov MC97F60128
382 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
292
MC97F60128
ADCCRH (A/D Converter High Register) : 4003H (XSFR)
7
6
5
4
3
2
1
0
ADCIE
ADCIFR
TRIG2
TRIG1
TRIG0
ALIGN
CKSEL1
CKSEL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
ADCIE
Enable or Disable A/DC Interrupt
0
Disable
1
Enable
ADCIFR
When ADC interrupt occurs, this bit becomes 1. For clearing bit, write 0 to this bit or
auto clear by INT_ACK signal. Write 1 has no effect.
0
ADC Interrupt no generation
1
ADC Interrupt generation
TRIG[2:0]
A/D Trigger Signal Selection
TRIG2
TRIG1
TRIG0
Description
0
0
0
ADST
0
0
1
Timer 3 A match signal
0
1
0
Timer 4 A match signal
0
1
1
Timer 5 A match signal
1
0
0
Timer 8 overflow event signal
1
0
1
Timer 8 A match event signal
1
1
0
Timer 8 B match event signal
1
1
1
Timer 8 C match event signal
ALIGN
A/D Converter data align selection.
0
MSB align (ADCDRH[7:0], ADCDRL[7:4])
1
LSB align (ADCRDH[3:0], ADCDRL[7:0])
CKSEL[1:0]
A/D Converter Clock selection
CKSEL1
CKSEL0
Description
0
0
fx/1
0
1
fx/2
1
0
fx/4
1
1
fx/8

Table of Contents

Related product manuals