Abov MC97F60128 - Page 293

293
MC97F60128
ABOV Semiconductor Co., Ltd.
ADCCRL (A/D Converter Counter Low Register) : 4002H (XSFR)
7
6
5
4
3
2
1
0
STBY
ADST
-
AFLAG
ADSEL3
ADSEL2
ADSEL1
ADSEL0
R/W
R/W
-
R
R/W
R/W
R/W
R/W
Initial value : 00H
STBY
Control Operation of A/D
(The ADC module is automatically disabled at stop mode)
0
ADC module disable
1
ADC module enable
ADST
Control A/D Conversion Start.
0
No effect
1
Trigger signal generation for conversion start
AFLAG
A/D Converter Operation State (This bit is cleared to ‘0’ when the STBY bit is set to ‘0’
or when the CPU is at STOP mode)
0
During A/D Conversion
1
A/D Conversion finished
ADSEL[3:0]
A/D Converter input selection
ADSEL3
ADSEL2
ADSEL1
ADSEL0
Description
0
0
0
0
AN0
0
0
0
1
AN1
0
0
1
0
AN2
0
0
1
1
AN3
0
1
0
0
AN4
0
1
0
1
AN5
0
1
1
0
AN6
0
1
1
1
AN7
1
0
0
0
AN8
1
0
0
1
AN9
1
0
1
0
AN10
1
0
1
1
AN11
1
1
0
0
AN12
1
1
0
1
AN13
1
1
1
0
AN14
1
1
1
1
VDD18