Abov MC97F60128 - Page 316

316
MC97F60128
ABOV Semiconductor Co., Ltd.
LCDCRL (LCD Driver Control Low Register) : 400AH (XSFR)
7
6
5
4
3
2
1
0
-
-
-
DBS2
DBS1
DBS0
LCLK1
LCLK0
-
-
-
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
DBS[2:0]
LCD Duty and Bias Select
DBS2
DBS1
DBS0
Description
0
0
0
1/8Duty, 1/4Bias
0
0
1
1/6Duty, 1/4Bias
0
1
0
1/5Duty, 1/3Bias
0
1
1
1/4Duty, 1/3Bias
1
0
0
1/3Duty, 1/3Bias
1
0
1
1/3Duty, 1/2Bias
1
1
0
1/2Duty, 1/2Bias
1
1
1
Not available
LCLK[1:0]
LCD Clock Select (When f
WCK
(Watch timer clock)= 32.768 kHz)
LCLK1
LCLK0
Description
0
0
f
LCD
= 128Hz
0
1
f
LCD
= 256Hz
1
0
f
LCD
= 512Hz
1
1
f
LCD
= 1024Hz (* NOTE)
NOTE)
1. When the fLCD is 1024Hz, LCD automatic bias control (bias
mode A/B) is disabled