Abov MC97F60128 - Page 340

340
MC97F60128
ABOV Semiconductor Co., Ltd.
Figure 13.5 Configuration Timing when Power-on
VDD
Internal nPOR
PAD RESETB
BIT (for Config)
LVR_RESETB
BIT (for Reset)
INT-OSC 8MHz/8
INT-OSC (8MHz)
RESET_SYSB
Config Read
1us X 256 X 28h = about 10ms
1us X 4096 X 4h = about 16ms
00
01
02
03
00
..
27
28
F1
Counting for config read start after POR is released
“H”
INT-OSC 8MHz / 8 = 1MHz (1us)
00
01
01
02
03
04
05
00