Abov MC97F60128 - Page 381

381
MC97F60128
ABOV Semiconductor Co., Ltd.
11.15.9 DAC Register Description .................................................................................................................... 299
11.15.10 Register Description for DAC ............................................................................................................... 300
11.16 LCD Driver .................................................................................................................................................. 304
11.16.1 Overview .............................................................................................................................................. 304
11.16.2 LCD Display RAM Organization .......................................................................................................... 305
11.16.3 LCD Signal Waveform ......................................................................................................................... 306
11.16.4 LCD Voltage Dividing Connection ........................................................................................................ 310
11.16.5 LCD AUTOMATIC BIAS CONTROL .................................................................................................... 313
11.16.6 Block Diagram ...................................................................................................................................... 314
11.16.7 Register Map ........................................................................................................................................ 315
11.16.8 LCD Driver Register Description .......................................................................................................... 315
11.16.9 Register Description for LCD Driver .................................................................................................... 315
11.17 The Fine ADPCM Decoder ......................................................................................................................... 319
11.17.1 Overview .............................................................................................................................................. 319
11.17.2 Function Description ............................................................................................................................ 319
11.17.3 The Decoder Result Output of the FADPCM ....................................................................................... 320
11.17.4 Serial Flash Interface by SPI2 or SPI3 ................................................................................................ 321
11.17.5 Voice Prompt Play................................................................................................................................ 322
11.17.6 Block Diagram ...................................................................................................................................... 324
11.17.7 Register Map ........................................................................................................................................ 325
11.17.8 FADPCM Register Description ............................................................................................................ 325
11.17.9 Register Description for FADPCM ....................................................................................................... 326
12. Power Down Operation .................................................................................................................................... 332
12.1 Overview ......................................................................................................................................................... 332
12.2 Peripheral Operation in IDLE/STOP Mode ..................................................................................................... 332
12.3 IDLE Mode ...................................................................................................................................................... 333
12.4 STOP Mode .................................................................................................................................................... 334
12.5 Release Operation of STOP Mode ................................................................................................................. 335
12.6 Register Map .................................................................................................................................................. 336
12.7 Power Down Operation Register Description ................................................................................................. 336
12.8 Register Description for Power Down Operation ............................................................................................ 336
13. RESET................................................................................................................................................................ 337
13.1 Overview ......................................................................................................................................................... 337
13.2 Reset Source .................................................................................................................................................. 337
13.3 RESET Block Diagram ................................................................................................................................... 337
13.4 RESET Noise Canceller ................................................................................................................................. 338
13.5 Power on RESET ............................................................................................................................................ 339
13.6 External RESETB Input .................................................................................................................................. 342
13.7 Brown Out Detector Processor ....................................................................................................................... 343
13.8 LVI Block Diagram .......................................................................................................................................... 344
13.9 Register Map .................................................................................................................................................. 345
13.10 Reset Operation Register Description ........................................................................................................ 345
13.11 Register Description for Reset Operation ................................................................................................... 346
14. On-chip Debug System .................................................................................................................................... 349
14.1 Overview ......................................................................................................................................................... 349
14.1.1 Description ............................................................................................................................................... 349
14.1.2 Feature .................................................................................................................................................... 350
14.2 Two-Pin External Interface.............................................................................................................................. 351
14.2.1 Basic Transmission Packet ..................................................................................................................... 351
14.2.2 Packet Transmission Timing .................................................................................................................... 352
14.2.2.1 Data Transfer ................................................................................................................................................... 352
14.2.2.2 Bit Transfer ...................................................................................................................................................... 352
14.2.2.3 Start and Stop Condition .................................................................................................................................. 353
14.2.2.4 Acknowledge Bit .............................................................................................................................................. 353
14.2.3 Connection of Transmission .................................................................................................................... 354
14.2.4 Circuit ...................................................................................................................................................... 354
15. Flash Memory ................................................................................................................................................... 355