Abov MC97F60128 - Page 74

74
MC97F60128
ABOV Semiconductor Co., Ltd.
SINTCR (System Interrupt Control Register) : F7H
7
6
5
4
3
2
1
0
–
–
–
SPOVIE
–
–
–
SPOVIFR
–
–
–
R/W
–
–
–
R/W
Initial value : 00H
SPOVIE
Stack Pointer Overflow Interrupt
0
Disable
1
Enable
SPOVIFR
When SPOVF Interrupt occurs, this bit becomes ‘1’. The flag
is cleared only by writing a ‘0’ to the bit. So, the flag should
be cleared by software.
0
Stack pointer overflow Interrupt no generation
1
Stack pointer overflow Interrupt generation
NOTE)
1. When the XSPEN bit of the XSPCR register is “0b”
- The stack pointer (SP) register is compared to the stack pointer watch low register (SWARL).
- If the values are same (SP[7:0] == SWARL[7:0]), the SPOVIFR bit is set to “1b”.
- At this time, the XSP and SWARH registers are don’t care.
2. When the XSPEN bit of the XSPCR register is “1b”
- The extended stack pointer and stack pointer (XSP:SP) registers are compared to the stack
pointer watch high and low register (SWARH:SWARL).
- If the values are same (XSP:SP[15:0] == SWARH:SWARL[15:0]), the SPOVIFR bit is set to “1b”.
XBANK (XRAM Bank Pointer) : F8H
7
6
5
4
3
2
1
0
XBANK
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
XBANK
XRAM Bank Pointer
NOTE)
1. This XBANK register holds the [15:8] part of memory address during access to data.
2. Address[15:0]: “XBANK:Ri” (Ri: R0 or R1)
3. Ex) MOVX A,@Ri ; Move external data (XBANK:Ri[15:0]) to A
MOVX @Ri,A ; Move A to external data (XBANK:Ri[15:0])