Abov MC97F60128 - Page 73

73
MC97F60128
ABOV Semiconductor Co., Ltd.
EO (Extended Operation Register) : A2H
7
6
5
4
3
2
1
0
–
–
–
TRAP_EN
–
DPSEL2
DPSEL1
DPSEL0
–
–
–
R/W
–
R/W
R/W
R/W
Initial value : 00H
TRAP_EN
Select the Instruction (Keep always ‘0’).
0
Select MOVC @(DPTR++), A
1
Select Software TRAP Instruction
DPSEL[2:0]
Select Banked Data Pointer Register
DPSEL2
DPSEL1
DPSEL0
Description
0
0
0
DPTR0
0
0
1
DPTR1
Reserved
SPWRL (Stack Pointer Watch Register Low Byte) : F4H
7
6
5
4
3
2
1
0
SPWRL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
SPWRL
Stack Pointer Watch Low
SPWRH (Stack Pointer Watch Register High Byte) : F5H
7
6
5
4
3
2
1
0
SPWRH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
SPWRH
Stack Pointer Watch High
MODINR (Mode Entry Register) : FFH
7
6
5
4
3
2
1
0
–
–
–
–
–
–
MODE1
MODE0
–
–
–
–
–
–
R/W
R/W
Initial value : 00H
DPSEL[1:0]
MCU MODE Indicator
MODE1
MODE0
Description
0
0
User Mode
0
1
OCD Mode
1
0
Runflag High Indicator, If the RUNFLAG pin is high level
During a power-on reset, the MODE[1:0] is set to “10b”
1
1
Not available