366
8331B–AVR–03/12
Atmel AVR XMEGA AU
Figure 28-16. ADC timing for single conversion on two ADC channels, CH0 with gain.
28.9.5 Single Conversions on Two ADC Channels, CH1 with Gain
Figure 28-17 on page 366 shows the conversion timing for single conversions on two ADC chan-
nels where ADC channel 1 uses the gain stage.
Figure 28-17. ADC timing for single conversion on two ADC channels, CH1 with gain.
28.9.6 Free Running Mode on Two ADC Channels with Gain
Figure 28-18 on page 367 shows the conversion timing for all four ADC channels in free running
mode, CH0 and CH1 without gain and CH2 and CH3 with gain. When set up in free running
mode, an ADC channel will continuously sample and do new conversions. In this example, all
ADC channels are triggered at the same time, and each ADC channel samples and start con-
verting as soon as the previous ADC channel is done with its sample and msb conversion. After
four ADC clock cycles, all ADC channels have done the first sample and started the first conver-
sion, and each ADC channels can then do the sample conversion start for their second
conversion. After eight (for 12-bit mode) ADC clock cycles, the first conversion is done for ADC
channel 0, and the results for the rest of the ADC channels are available in subsequent ADC
clock cycles. After the next clock cycle (in cycle 10), the result from the second ADC channel is
START CH1, wo/GAIN
ADC SAMPLE
IF CH1
START CH0, w/GAIN
IF CH0
GAINSTAGE SAMPLE
GAINSTAGE AMPLIFY
CONVERTING BIT CH0
CONVERTING BIT CH1
MSB 10 9 8 7
6
5 4 3 2 1 LSB
MSB 10 9
8
7
6
5
4 3 2
1
LSB
CLK
ADC
12345678
9
10
START CH1, w/GAIN
ADC SAMPLE
IF CH1
CONVERTING BIT CH0
START CH0, wo/GAIN
IF CH0
CONVERTING BIT CH1
GAINSTAGE SAMPLE
GAINSTAGE AMPLIFY
CLK
ADC
12345678
9
10
MSB
10
9 8 7 6 5 4 3 2 1 LSB
MSB
10 9
8 7 6 5 4 3 2 1 LSB
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