94
8331B–AVR–03/12
Atmel AVR XMEGA AU
7.9.3 LOCK – Lock register
• Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 0 – LOCK: Clock System Lock
When this bit is written to one, the CTRL and PSCTRL registers cannot be changed, and the
system clock selection and prescaler settings are protected against all further updates until after
the next reset. This bit is protected by the configuration change protection mechanism. For
details, refer to ”Configuration Change Protection” on page 13.
The LOCK bit can be cleared only by a reset.
7.9.4 RTCCTRL – RTC Control register
• Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:1 – RTCSRC[2:0]: RTC Clock Source
These bits select the clock source for the real-time counter according to Table 7-4.
Bit 76543210
+0x02 – – – – – – – LOCK LOCK
Read/WriteRRRRRRRR/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
+0x03 – – – – RTCSRC[2:0] RTCEN RTCCTRL
Read/WriteRRRRR/WR/WR/WR/W
Initial Value00000000
Table 7-4. RTC clock source selection.
RTCSRC[2:0] Group Configuration Description
000 ULP 1kHz from 32kHz internal ULP oscillator
001 TOSC 1.024kHz from 32.768kHz crystal oscillator on TOSC
010 RCOSC 1.024kHz from 32.768kHz internal oscillator
011 — Reserved
100 — Reserved
101 TOSC32 32.768kHz from 32.768kHz crystal oscillator on TOSC
110 RCOSC32 32.768kHz from 32.768kHz internal oscillator
111 EXTCLK External clock from TOSC1
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