Cypress PSoC 4000 Series - Page 6

6 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Contents
4.7.1 Address Alignment ................................................................................................29
4.7.2 Memory Endianness..............................................................................................29
4.8 Systick Timer..........................................................................................................................29
4.9 Debug.....................................................................................................................................29
5. Interrupts 31
5.1 Features .................................................................................................................................31
5.2 How It Works ..........................................................................................................................31
5.3 Interrupts and Exceptions - Operation....................................................................................32
5.3.1 Interrupt/Exception Handling .................................................................................32
5.3.2 Level and Pulse Interrupts.....................................................................................32
5.3.3 Exception Vector Table ..........................................................................................33
5.4 Exception Sources..................................................................................................................33
5.4.1 Reset Exception ....................................................................................................33
5.4.2 Non-Maskable Interrupt (NMI) Exception ..............................................................34
5.4.3 HardFault Exception ..............................................................................................34
5.4.4 Supervisor Call (SVCall) Exception .......................................................................34
5.4.5 PendSV Exception.................................................................................................34
5.4.6 SysTick Exception .................................................................................................35
5.5 Interrupt Sources....................................................................................................................35
5.6 Exception Priority....................................................................................................................35
5.7 Enabling and Disabling Interrupts...........................................................................................36
5.8 Exception States.....................................................................................................................36
5.8.1 Pending Exceptions...............................................................................................36
5.9 Stack Usage for Exceptions ...................................................................................................37
5.10 Interrupts and Low-Power Modes...........................................................................................37
5.11 Exceptions – Initialization and Configuration..........................................................................38
5.12 Registers ................................................................................................................................38
5.13 Associated Documents...........................................................................................................38
Section C: Memory System 39
6. Memory Map 41
6.1 Features .................................................................................................................................41
6.2 How It Works ..........................................................................................................................41
Section D: System Resources Subsystem (SRSS) 43
7. I/O System 45
7.1 Features .................................................................................................................................45
7.2 GPIO Interface Overview........................................................................................................45
7.3 I/O Cell Architecture ...............................................................................................................46
7.3.1 Digital Input Buffer .................................................................................................47
7.3.2 Digital Output Driver ..............................................................................................48
7.4 High-Speed I/O Matrix...........................................................................................................51
7.5 I/O State on Power Up............................................................................................................51
7.6 Behavior in Low-Power Modes...............................................................................................51
7.7 Interrupt..................................................................................................................................51
7.8 Peripheral Connections ..........................................................................................................53
7.8.1 Firmware Controlled GPIO ....................................................................................53
7.8.2 CapSense..............................................................................................................53
7.8.3 Timer, Counter, and Pulse Width Modulator (TCPWM) Block ...............................53
7.9 Registers ................................................................................................................................53