Cypress PSoC 4000 Series - Page 7

PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 7
Contents
8. Clocking System 55
8.1 Block Diagram ........................................................................................................................55
8.2 Clock Sources.........................................................................................................................56
8.2.1 Internal Main Oscillator ..........................................................................................56
8.2.2 Internal Low-speed Oscillator ................................................................................57
8.2.3 External Clock (EXTCLK) ......................................................................................57
8.3 Clock Distribution....................................................................................................................57
8.3.1 HFCLK Input Selection ..........................................................................................57
8.3.2 HFCLK Predivider Configuration............................................................................58
8.3.3 SYSCLK Prescaler Configuration ..........................................................................58
8.3.4 Peripheral Clock Divider Configuration..................................................................58
8.4 Low-Power Mode Operation.............................................................................................59
8.5 Register List............................................................................................................................59
9. Power Supply and Monitoring 61
9.1 Block Diagram ........................................................................................................................62
9.2 Power Supply Scenarios.........................................................................................................63
9.2.1 Single 1.8 V to 5.5 V Unregulated Supply..............................................................63
9.2.2 Direct 1.71 V to 1.89 V Regulated Supply .............................................................63
9.2.3 VDDIO Supply........................................................................................................64
9.3 How It Works ..........................................................................................................................64
9.3.1 Regulator Summary...............................................................................................64
9.4 Voltage Monitoring..................................................................................................................65
9.4.1 Power-On-Reset (POR).........................................................................................65
9.5 Register List ...........................................................................................................................65
10. Chip Operational Modes 67
10.1 Boot ........................................................................................................................................67
10.2 User ........................................................................................................................................67
10.3 Privileged................................................................................................................................67
10.4 Debug .....................................................................................................................................67
11. Power Modes 69
11.1 Active Mode............................................................................................................................70
11.2 Sleep Mode.............................................................................................................................70
11.3 Deep-Sleep Mode...................................................................................................................70
11.4 Power Mode Summary ...........................................................................................................71
11.5 Low-Power Mode Entry and Exit ............................................................................................72
11.6 Register List............................................................................................................................72
12. Watchdog Timer 73
12.1 Features..................................................................................................................................73
12.2 Block Diagram ........................................................................................................................73
12.3 How It Works ..........................................................................................................................73
12.3.1 Enabling and Disabling WDT.................................................................................74
12.3.2 WDT Interrupts and Low-Power Modes.................................................................75
12.3.3 WDT Reset Mode ..................................................................................................75
12.4 Register List ..........................................................................................................................75
13. Reset System 77
13.1 Reset Sources ........................................................................................................................77
13.1.1 Power-on Reset .....................................................................................................77
13.1.2 Brownout Reset .....................................................................................................77