Cypress PSoC 4000 Series - Page 8

8 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Contents
13.1.3 Watchdog Reset ....................................................................................................77
13.1.4 Software Initiated Reset.........................................................................................78
13.1.5 External Reset.......................................................................................................78
13.1.6 Protection Fault Reset...........................................................................................78
13.2 Identifying Reset Sources.......................................................................................................78
13.3 Register List............................................................................................................................78
14. Device Security 79
14.1 Features .................................................................................................................................79
14.2 How It Works ..........................................................................................................................79
14.2.1 Device Security......................................................................................................79
14.2.2 Flash Security........................................................................................................80
Section E: Digital System 81
15. Inter-Integrated Circuit (I2C) 83
15.1 Features .................................................................................................................................83
15.2 General Description................................................................................................................83
15.2.1 Terms and Definitions............................................................................................84
15.2.2 I2C Modes of Operation ........................................................................................84
15.2.3 Easy I2C (EZI2C) Protocol ....................................................................................86
15.2.4 I2C Registers.........................................................................................................87
15.2.5 I2C Interrupts.........................................................................................................88
15.2.6 Enabling and Initializing the I2C ............................................................................88
15.2.7 Internal and External Clock Operation in I2C ........................................................89
15.2.8 Wake up from Sleep ..............................................................................................91
15.2.9 Master Mode Transfer Examples...........................................................................92
15.2.10 Slave Mode Transfer Examples.............................................................................94
15.2.11 EZ Slave Mode Transfer Example.........................................................................96
15.2.12 Multi-Master Mode Transfer Example....................................................................98
16. Timer, Counter, and PWM 101
16.1 Features ...............................................................................................................................101
16.2 Block Diagram ......................................................................................................................101
16.2.1 Enabling and Disabling Counter in TCPWM Block..............................................102
16.2.2 Clocking...............................................................................................................102
16.2.3 Events Based on Trigger Inputs...........................................................................103
16.2.4 Output Signals.....................................................................................................104
16.2.5 Power Modes.......................................................................................................105
16.3 Modes of Operation..............................................................................................................106
16.3.1 Timer Mode..........................................................................................................107
16.3.2 Capture Mode...................................................................................................... 110
16.3.3 Quadrature Decoder Mode.................................................................................. 112
16.3.4 Pulse Width Modulation Mode............................................................................. 115
16.3.5 Pulse Width Modulation with Dead Time Mode ................................................... 119
16.3.6 Pulse Width Modulation Pseudo-Random Mode.................................................121
16.4 TCPWM Registers................................................................................................................123
Section F: Analog System 125
17. CapSense 127
17.1 Features ...............................................................................................................................127
17.2 Block Diagram ......................................................................................................................127
17.3 How It Works ........................................................................................................................128