Cypress PSoC 4000 Series - Page 9

PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 9
Contents
17.4 CapSense CSD Sensing ......................................................................................................129
17.4.1 GPIO Cell Capacitance to Current Converter ......................................................129
17.4.2 CapSense Clock Generator.................................................................................131
17.4.3 Sigma Delta Converter.........................................................................................131
17.5 CapSense CSD Shielding.....................................................................................................133
17.5.1 CMOD Precharge ................................................................................................134
17.6 General-Purpose Resources: IDACs and Comparator.........................................................135
17.7 Register List..........................................................................................................................135
Section G: Program and Debug 137
18. Program and Debug Interface 139
18.1 Features................................................................................................................................139
18.2 Functional Description ..........................................................................................................139
18.3 Serial Wire Debug (SWD) Interface......................................................................................140
18.3.1 SWD Timing Details.............................................................................................141
18.3.2 ACK Details..........................................................................................................141
18.3.3 Turnaround (Trn) Period Details ..........................................................................141
18.4 Cortex-M0 Debug and Access Port (DAP) ...........................................................................142
18.4.1 Debug Port (DP) Registers ..................................................................................142
18.4.2 Access Port (AP) Registers ................................................................................142
18.5 Programming the PSoC 4 Device.........................................................................................143
18.5.1 SWD Port Acquisition...........................................................................................143
18.5.2 SWD Programming Mode Entry...........................................................................143
18.5.3 SWD Programming Routines Executions ............................................................143
18.6 PSoC 4 SWD Debug Interface .............................................................................................144
18.6.1 Debug Control and Configuration Registers ........................................................144
18.6.2 Breakpoint Unit (BPU)..........................................................................................144
18.6.3 Data Watchpoint (DWT).......................................................................................144
18.6.4 Debugging the PSoC 4 Device ............................................................................144
18.7 Registers...............................................................................................................................145
19. Nonvolatile Memory Programming 147
19.1 Features................................................................................................................................147
19.2 Functional Description ..........................................................................................................147
19.3 System Call Implementation.................................................................................................148
19.4 Blocking and Non-Blocking System Calls.............................................................................148
19.4.1 Performing a System Call ....................................................................................148
19.5 System Calls.........................................................................................................................149
19.5.1 Silicon ID..............................................................................................................149
19.5.2 Configure Clock ...................................................................................................150
19.5.3 Load Flash Bytes .................................................................................................151
19.5.4 Write Row ............................................................................................................152
19.5.5 Program Row.......................................................................................................152
19.5.6 Erase All...............................................................................................................153
19.5.7 Checksum............................................................................................................153
19.5.8 Write Protection ...................................................................................................154
19.5.9 Non-Blocking Write Row......................................................................................155
19.5.10 Non-Blocking Program Row.................................................................................156
19.5.11 Resume Non-Blocking .........................................................................................157
19.6 System Call Status ...............................................................................................................158
19.7 Non-Blocking System Call Pseudo Code .............................................................................159
Glossary 161