Intel MCS 51 User Manual

i~.
MCS”-51 programmers GUIDE AND INSTRUCTION SET
XCHD A,@Ri
Funotion:
Example:
Bytes:
cycles:
Encoding:
Operation:
ExchangeDigit
XCHDexchangesthe low-ordernibbleof the Accumulator(bits3-O),generallyrepresentinga
hexadecimalorBCD digit,withthat ofthe internal IGUkilocationindirectlyaddressedbythe
sapp~ti=gister. me high-ordernibbles(bits 7-4)of each registerare not af%cted.No tlsgs
ROcontains the address 20H.The A
ccunndatorholds the value36H (OO11O1IOB).Internal
W location20H holdsthe value75H(O111O1O1B).The instruction,
XCHD A,@RO
willleaveRAM location20Hholdingthe value76H(O111O11OB)and 35H(OIM1O1O1B)inthe
Accumulator.
1
1
1101 Olli
XCHD
(A~~) Z ((lti~~))
XRL <cleat-byte>, <src-byte>
Function:
Logical
Exclusive-ORforbytevsriablea
Description:
XRL performs the bitwiselogicalExcIusive-ORoperationbetweenthe indicated variables,
storingthe results in the destination.No flagsare affected.
Thetwooperandsallowsixaddressingmodecombinations.Whenthe destinationis the Accu-
mulator, the source can use register,direcLregister-indirect,or immediateaddressing;when
the destinationis a direct address,the source can be the Accumulatoror immediatedata.
(Note When this instructionis usedto modifyan output port, the value usedas the original
port dats willbe read fromthe output data latch, not the input pins.)
Example:
If the AccumulatorholdsOC3H(11000011B)and registerOholdsOAAH(101OIO1OB)then
the instruction,
XRL A,RO
willleavethe Accumulator
holdingthe vatue69H (O11OIOOIB).
Whenthe destinationis a directlyaddressedbyte thisinstructioncan complementcombina-
tionsofbitsinanyMM locationorhardwareregister.Thepatternofbitstobecomplement-
ed is thendetermin
ed bya maskbyte eithera constsntcontainedin the instructionor a
variablecomputedin theAccumulatorat run-time.Theinstruction,
XRL
Pl,#OOllOOOIB
willcomplementbits 5, 4, and Oof output Port 1.
2-73

Intel MCS 51 Specifications

General

Brand	Intel
Model	MCS 51
Category	Microcontrollers
Language	English