i~o
83C152 HARDWAREDESCRIPTION
3.7 Register Descriptions
ADR0,1,2,3 (95H, OA5H,OB5H,OC5H)- Address
Match Registers0,1,2,3- contains the address match
valueawhichdetermineswhichdata willbeacceptedas
valid.In 8bit addressingmode,a match withanyofthe
four registerswilltriggeracceptance.In 16bit address-
ingmodea matchwithADRIADRO or ADR3:ADR2
will be accepted. Addressingmode is determm
“edirr
GMOD (AL).
AMSKO,l(OD5H,OE5H)- AddressMatch Mask0,1-
Identifieswhichbits in ADRO,lare “don’tcare” bits.
Writing a one to a bit in AMSKO,l masks out that
correspondingbit in ADDRO,l.
BAUD (94H)- GSCBaudRate Generator - Contains
the valueof the programmablebaud rate. Thedata rate
will equal (frequencyof the oscillator)/((BAUD + 1)
x (8)).Writingto BAUDactuallystoreathe vahe ina
reload register.The reloadregistercontentsare copied
into the BAUDregisterwhenthe Baud registerdeere-
mentato OOH.ReadingBAUDyieldsthe current timer
value. A read during GSCoperation will givea value
that maynot be current becausethe timer mold decm
mentbetweenthe timeit is read bythe CPUandbythe
time the valueis loadedintoits destination.
BKOFF (OC4H)- BaekoffTimer- Thebackofftimeris
an eightbit countdowntimerwitha clockperiodequal
to one slot time. The backoff time is used in the
CSMA/CD eollisiott resolutionalgorithm. The user
softwaremayread thetimerbutthe valuemaybeinval-
id as the timer is clockedasynchronouslyto the CPU.
Writingto OC4Hwillhaveno effeet.
GMOD(84H)
7 6543210
XTCLK
Ml MO AL CT PL1 PLO PR
Rgure 3.14. GMOD
GMOD.O(PR)- Protocol-If set, SDLCprotocolswith
NRZI encodingand SDLCflags are used. If cleared,
CSMA/CD link
access with Manchester encodingis
used. The user sotl,wareis responsiblefor setting or
Clearing
this flag.
GMOD.1,2(PLO,l)- Preamblelength
PL1 PLOLENGTH(BITS)
000
018
1 0 32
1164
Thelengthincludesthe twobit BeginOfFrame (BOF)
tlagin CSMA/CDbut doeanot includethe SDLCflag.
In SDLCmode,the BOFis an SDLCflag,otherwiseit
is two co
naecutiveones.Zero lengthis not compatible
in CSMA/CD mode.The user softwareis responsible
for settingor cl
earingthese bits.
GMOD.3(CT)- CRCType-If set,32bit AUTODIN-
11-32is used. If clear~ 16bit CRC-CCITTis used.
The user softwareis responsiblefor settingor clearing
this tlag.
GMOD.4 (AL) - Address Lestgth- If set, 16bit ad-
dressingisused.If cleared,8bit addressingis used.In 8
bit mode a match with any of the 4 address registers
will be accepted (ADRO, ADR1, ADR2, ADR3).
“Don’tCare”bitsmaybemaskedinADROand ADRI
with AMSKOand AMSK1.In 16bit mode,addreases
are matched againat “ADR1:ADRO”or “ADR3:
ADR2”. Again,
“Don’t Care” bits in ADRIA.DRO
canbemaskedin AMSK1:AMSKO.A receivedaddress
ofall oneswillalwaysbe recognizedin any mode.The
user softwareis responsiblefor settingor clearingthis
tlag.
GMOD.5,6~O,Ml) - ModeSelect- Twotest modes,
=
OPtiOtd “alternate backoff’mode,or normalback.
off can be enabledwith these two bits. The user aoft-
wareis responsiblefor settingor clearingthe modebita.
Ml MO Mcde
o 0 Normal
o
1 RSWTransmit
1 0 RawReceive
1 1 Alternate Backoff
In raw receivemod%the receiveroperateaas normal
exeeptthat all the byte-sfollowingthe BOFare loaded
into the receiveFIFO, includingthe CRC.The trans-
mitter operatesas normal.
In raw transmit modethe transmitoutputis internally
connectedto the reeeiver input. The internal c4mnec-
timt is not at the acturd port pin, but inside the port
latch. All data transmitted is donewithouta preamble,
flag or zero bit insertion, and without appending a
CRC. The receiveroperates as normal.Zero bit delet-
ion is performed.
In alternatebackoffmodethe standardbackoffproeeas
ismodifiedsothe the baekoffis delayeduntil the endof
the IFS. This should help to prevent collisionscon-
stantlyhappeningbecausethe IFStimeisusuallylarger
than the slot time.
7-44
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