i@.
McS@-51PROGRAMMER’SGUIDEAND INSTRUCTION SET
T2CON: TIMER/COUNTER 2 CONTROL REGISTER. BIT ADDRESSABLE
8052 Only
TF2 EXF2
RCLK
TCLK
EXEN2 TR2
Cln cP/m
TP2
EXP2
RCLK
TLCK
EXEN2
TR2
CRT
T2CON.7 Timer 2 overfiowtlag set by hardwareand cleared by software.
either RCLK = 1or CLK = 1
TP2 cannotbe setwhen
T2CON.6 Timer2 externalfig set wheneithera c.mtureor reloadiscausedbva nemtivetransitionon
T2C0N. 5
T2C0N. 4
T2C0N. 3
T2CON.2
T2CON.1
cP/Rm T2CON.o
T2EX,andEXEN2-= 1.WhenTimer2ktermpt isenabl~ EXF2-= 1‘%11causethe CPU
to vectorto the Timer 2 interrupt routine.EXF2must be clearedby software
Receiveclock tlag. When set, causesthe SerialPort to use Timer 2 overtlowpulsesfor its
receiveclockin modes 1& 3. RCLK = OcausesTimer 1overflowto be usedfor the receive
clock.
Transmit clockflag. When set, causesthe SerialPort to useTimer 2 overtlowpulsesfor its
transmit clock in modes 1 & 3. TCLK = Ocauses Timer 1 overflowsto be used for the
transmit clcck.
Timer 2 external enableflag. Whenset, allowsa capture or reload to occur as a result of
negativetransition on T2EX if Timer 2 is not being used to clock the Serial Port.
EXEN2 = OcauaeaTimer 2 to ignoreeventsat T2EX.
SoftwareSTART/STOPcontrolforTimer 2. A logic 1starts the Timer.
Timer or Counterselect.
O = Internal Timer. 1 = ExternalEventCounter(fallingedgetriggered).
Capture/Reload flag. Whereset, captures will occur on negative transitions at T2EX if
EXEN2 = 1. When cleared, AuteReloads will occur either with Timer 2 overflowsor
negativetransitionsat TZEXwhenEXEN2 = 1.Wheneither RCLK = 1or TCLK = 1,
this bit is ignoredand the Timeris forcedto Auto-Reloadon Timer 2 overflow.
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