intdo
HARDWARE DESCRIPllON OFTHE 8051,8052 AND 80C51
completedbeforevectoringto anyserviceroutine.Con-
dition 3 ensures that if the instruction in progress is
RETI or any accessto IE or 1P,then at least
one more
instructionwiffbeexecutedbeforeanyinterrupt is vec-
tored to.
The
polfing cycleis repeatedwith eachmachinecycl~
and the valuespolledarethe valuesthat werepresentat
S5P2of the previousmachinecycle. Note then that if
an interruptflagisactivebut not beingrespondedto for
oneofthe aboveconditions,and is not
still active when
the blockingconditionis removed,the deniedinterrupt
will not be serviced.In other wor& the fact that the
interrupt tlag was once active but not servicedis not
remembemd.Everypoflingcycleis new.
The pofling cycle/LCALL sequence is illustrated in
Figure 24.
Note that if an interrupt of higher priority Ievefgoes
activeprior to S5P2ofthe machinecyclelabeledC3in
Figure 24, then in accordancewith the aboverules it
@ be
Vectored to duringC5 and cd, withoutStlyin-
struction of the lowerpriority routinehavingbeenexe-
cuted.
Thus the procesaor acknowledgesan interrupt request
by executinga hardware-generatedLCALLto the ap
propriate servicingroutine.In somecasesit alsoclears
the flagthat generatedthe interrupt, and in other cases
it doesn’t. It never clears the Serial Port or Timer 2
flags. This has to be done in the user’s software. It
clears an externalinterrupt flag (IEOor IEl) onlyif it
was transition-activated. The hardware-generated
LCALL pushesthe contents of the Program Counter
onto the stack (but
itdoes not savethe PSW)and re-
loads the PC with an address that depends on the
sourceof the interruptbeingvectoredto, as ahownbe-
low.
8ource
Vector
Address
IEO OO03H
TFO
OOOBH
IE1
O013H
TF1 OOIBH
RI + TI O023H
TF2+ EXF2 O02BH
Executionproceedsfromthat locationuntiltheRETI
instructionis encountered.The RETIinstructionin-
formsthe processor
that this interruptroutineis no
longerinprogr~ thenpopsthe top twobyteafromthe
stack and reloadsthe program Counter.Executionof
the interrupted program continues from where it left
off.
Note that a simpleRET instruction wouldalso have
returned executionto the interrupted progmrn,but it
would have left the interrupt control systemthinking
an interrupt wasstiIlin progress.
ExternalInterrupts
Theexternalsourcescan beprogrammedto belevel-ac-
tivatedor transition-activatedby settingor clearingbit
ITI or ITOin Register TCON. If ITx = O,extemaf
interrupt x is triggeredby a detectedlowat the INTx
pin. If ITx = 1,external interruptx is edge-tiered.
In this mode if successi
ve samplesof the INTx pin
showa high in one cycleand a lowin the next CYCIG
interrupt requeatflag IEx in TCONis set. Flagbit IEx
then requeststhe interrupt.
Sincethe extemafinterrupt pinsare sampledonceeach
machinecycle,an input highor lowshouldhold for at
least 12 oscillator periods to ensure sampfing.If the
external interrupt is transition-activated,the external
sourcehas to hold the requeatpin highfor at least one
machinecycle, and then hold it low for at least one
machinecycle to ensure that the transition is seen so
that interrupt request flag IEx willbe set. IEx will be
automatically cleared by the CPU when the service
routineis called.
If the external interrupt is level-activated,the external
sourcehas to holdthe requestactiveuntilthe
requested
interrupt is actually generated.Then it has to deacti-
vate the request beforethe interrupt serviceroutine is
complet~ or else another interruptwillbe generated.
ResponseTime
The ~ and INT1 levelsare inverted and latched
into the interrupt tlags IEOand IEl
at S5P2of every
machineCycle.Similarly,the Timer 2 flag EXF2 and
the Serial Port flags RI and TI are set at S5P2.The
valuesare not actuallypolledbythe circuitry until the
next machinecycle.
TheTimerOand Timer 1flags,TFOandTFl, are set at
S5P2of the cycle in whichthe timers overflow.The
vafuesarethen polledbythecircuitryin the next cycle.
However,the Timer 2 flagTF2 is set at S2P2and is
polledin the same cyclein whichthe timer overtlows.
If a requeatis activeandconditionsare right for it to be
acknowledged,a hardware subroutinecd to the re-
questedserviceroutinewittbethenextinstructionto be
executed.The call itselftakestwocycles.Thus, a mini-
mum
ofthreecompletemachinecycleselapsebetween
activationof an externalinterrupt request and the be-
ginningofexecutionof the firstinstructionofthe aerv-
iceroutine.Figure24showsinterruptresponsetimings.
A longer responsetime woufdresult if the request is
blockedby one of the 3 previouslyfistedconditions.If
an interrupt of equalor higherprioritylevelis already
in progress,the additionalwaittimeobviouslydepends
onthe nature ofthe other interrupt’sserviceroutine. If
the instructionin progressis not in its final cycl~ the
additionalwaittimecannotbemorethan 3cycles,since
the longest instructions (MUL and DIV) are only 4
3-25
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