i~o
HARDWAREDESCRIPTION OFTHE 8051,8052 AND 80C51
Table 3. Reset Values of the SFRS
I
SFR Name Reset Value
Pc OOOOH
ACC
OOH
B OOH
Psw OOH
SP
07H
I DPTR I OOOOH I
I PO-P3 I FFH I
1P(8051)
XXXOOOOOB
1P(8052) XXOOOOOOB
IE [8051) OXXOOOOOB
1
IE (8052)
OXOOOOOOB
TMOD OOH
TCON
OOH
THO OOH
TLO
OOH
TH1
OOH
I TL1 I OOH I
[
TH2 (8052)
I
OOH
J
TL2
(8052)
OOH
RCAP2H(8052) OOH
RCAP2L(8052) OOH
SCON OOH
SBUF
Indeterminate
PCON (HMOS) OXXXXXXXB
PCON (CHMOS) OXXXOOOOB
,.”,l
k
UKIL
=
3
‘cc
Sml
ST
Isa
270252-21
Figure25.PoweronResetCircuit
POWER-ONRESET
ForHMOSdeviceswhenVCCisturnedonan automat-
ic reset can be obtainedby connectingthe RST pin to
V~ througha 10pF capacitorand to Vss throughan
8.2 Kf2 reeistor(Figure 26). The CHMOSdeviceado
not require this resistor althoughits presencedoeano
harm. In fact,forCHMOSdevicestheexternalresistor
canbe removedbecausethey havean internalpulldown
on the RSTpin.The capacitor valuecouldthen be r-
ducedto 1 pF.
Whenpoweristurned on,the circuitholdsthe RSTpin
highfor an amountoftime that dependson the capaci-
tor valueand the rate at whichit charges.To ensurea
validreset the RSTpin must beheldhighlongenough
to allow the oscillator to stsrt up plus two machine
cycles.
On power up, VCCshould rise within approximately
ten milliseconds.The oscillator start-up time will de-
pendonthe oscillatorfrequency.Fora 10MHz crystal,
thestart-uptimeis typically1rns.For a 1MHzcrystal,
the start-up time is typically 10ms.
Withthe givencircui~reducingVW quicklyto Ocaus-
es the RST pin voltageto momentarilyfall belowOV.
However,thisvoltageis internzdlylimitedand willnot
harm the device.
NOTE:
The port pins will be in a random state until
the oscillatorhas started and the internal reset
algorithmhas written 1sto them.
Poweringup the device without a valid reset could
causethe CPU to start executinginstructionsfrom an
indeterrninatelocation.This is becausethe SFRs, ape-
citicallythe Program Counter, may not get properly
initialized.
POWER-SAVINGMODESOF
OPERATION
For applicationswhere power consumptionis critical
the CHMOSversionprovideapowerreducedmodesof
operationas a standard feature.Thepowerdownmode
in HMOS
devicesisnolongerastandardfeatureandis
being
phasedOUt.
CHMOSPowerReductionModes
CHMOS versions have two power-reducingmodes,
Idle and PowerDown.The inputthroughwhichback-
up poweris suppliedduring these operationsis VCC.
Figure 27 shows the internal circuitry which imple-
mentsthesefeatures.In the Idle mode(IDL = 1),the
oscillator continueato run and the Interrupt, Serial
Port, and Timerblockscontinueto be clocked,but the
3-27
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