MCS@I-51 ARCHITECTURAL OVERVIEW
As soon as any priority 1 interrupt is acknowledged,
the IE (Interrupt Enable) register is m-defined so as to
disable all but “priority 2“ interrupts. Then, a CALL to
LAEEL exeoutes the RETI instruction, which clears
the priority 1 interrupt-in-program tlip-flop. At this
point SIly priority 1 interrupt that is enabled can be
seticed, but
Ody “priority’ 2“ illtCSTUptSare enabled.
POPping IE restores the original enable byte. Tberr a
normal RET (rather than another RETI) is used to
terminate the service routine. The additional software
adds 10 ps (at
12MHz) to priority 1 interrupts.
ADDITIONAL REFERENCES
The following application notes are found in the Em-
bedded Chstml AppIicatwns
handbook. (Order Num-
ber: 270648)
1. AP-69 “An Introduction
to the Intel MCS@-5I Sin.
gle-Chip Microcomputer Family”
2. AP-70 “Using the Intel MCW-51 Boolean Process-
ing Capabtities”
1-22
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